verilog计数器
256位计数器，题目：设计一个
8位计数器，包含清零信号 clear，复位信号 rst，预加载值 preload。
解答：
本次设置的
preload=32。理论上最大计数值为 256。模块名称为 counter。
文件下载
资源详情
[{"title":"（ 72 个子文件 133KB ） verilog计数器","children":[{"title":"counter.map.rpt <span style='color:#111;'> 21.59KB </span>","children":null,"spread":false},{"title":"counter.done <span style='color:#111;'> 26B </span>","children":null,"spread":false},{"title":"db","children":[{"title":"counter.lpc.html <span style='color:#111;'> 430B </span>","children":null,"spread":false},{"title":"counter.db_info <span style='color:#111;'> 153B </span>","children":null,"spread":false},{"title":"counter.tis_db_list.ddb <span style='color:#111;'> 188B </span>","children":null,"spread":false},{"title":"counter.map_bb.logdb <span style='color:#111;'> 4B </span>","children":null,"spread":false},{"title":"counter.lpc.rdb <span style='color:#111;'> 403B </span>","children":null,"spread":false},{"title":"counter.map.logdb <span style='color:#111;'> 4B </span>","children":null,"spread":false},{"title":"counter.hif <span style='color:#111;'> 771B </span>","children":null,"spread":false},{"title":"counter.map.hdb <span style='color:#111;'> 8.59KB </span>","children":null,"spread":false},{"title":"counter.sgdiff.cdb <span style='color:#111;'> 2.69KB </span>","children":null,"spread":false},{"title":"counter.cmp_merge.kpt <span style='color:#111;'> 216B </span>","children":null,"spread":false},{"title":"counter.map.kpt <span style='color:#111;'> 480B </span>","children":null,"spread":false},{"title":"counter.eda.qmsg <span style='color:#111;'> 2.33KB </span>","children":null,"spread":false},{"title":"counter.lpc.txt <span style='color:#111;'> 1.04KB </span>","children":null,"spread":false},{"title":"counter.cmp.hdb <span style='color:#111;'> 9.31KB </span>","children":null,"spread":false},{"title":"counter.cbx.xml <span style='color:#111;'> 89B </span>","children":null,"spread":false},{"title":"counter.(0).cnf.cdb <span style='color:#111;'> 2.24KB </span>","children":null,"spread":false},{"title":"prev_cmp_counter.qmsg <span style='color:#111;'> 2.30KB </span>","children":null,"spread":false},{"title":"counter.smart_action.txt <span style='color:#111;'> 8B </span>","children":null,"spread":false},{"title":"counter.sld_design_entry.sci <span style='color:#111;'> 212B </span>","children":null,"spread":false},{"title":"counter.pre_map.cdb <span style='color:#111;'> 2.37KB </span>","children":null,"spread":false},{"title":"counter.map.qmsg <span style='color:#111;'> 5.49KB </span>","children":null,"spread":false},{"title":"counter.pre_map.hdb <span style='color:#111;'> 8.34KB </span>","children":null,"spread":false},{"title":"counter.map.cdb <span style='color:#111;'> 2.81KB </span>","children":null,"spread":false},{"title":"counter.(0).cnf.hdb <span style='color:#111;'> 1.15KB </span>","children":null,"spread":false},{"title":"counter.cmp.rdb <span style='color:#111;'> 4.96KB </span>","children":null,"spread":false},{"title":"counter.rtlv.hdb <span style='color:#111;'> 8.33KB </span>","children":null,"spread":false},{"title":"counter.sld_design_entry_dsc.sci <span style='color:#111;'> 212B </span>","children":null,"spread":false},{"title":"counter.rtlv_sg.cdb <span style='color:#111;'> 2.00KB </span>","children":null,"spread":false},{"title":"counter.map_bb.hdb <span style='color:#111;'> 7.58KB </span>","children":null,"spread":false},{"title":"counter.hier_info <span style='color:#111;'> 1.40KB </span>","children":null,"spread":false},{"title":"counter.syn_hier_info <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"counter.map.bpm <span style='color:#111;'> 675B </span>","children":null,"spread":false},{"title":"logic_util_heursitic.dat <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"counter.map_bb.cdb <span style='color:#111;'> 1.07KB </span>","children":null,"spread":false},{"title":"counter.rtlv_sg_swap.cdb <span style='color:#111;'> 192B </span>","children":null,"spread":false},{"title":"counter.sgdiff.hdb <span style='color:#111;'> 8.44KB </span>","children":null,"spread":false}],"spread":false},{"title":"simulation","children":[{"title":"modelsim","children":[{"title":"counter_run_msim_rtl_verilog.do.bak2 <span style='color:#111;'> 479B </span>","children":null,"spread":false},{"title":"modelsim.ini <span style='color:#111;'> 10.82KB </span>","children":null,"spread":false},{"title":"counter_run_msim_rtl_verilog.do.bak <span style='color:#111;'> 479B </span>","children":null,"spread":false},{"title":"counter.vt <span style='color:#111;'> 3.19KB </span>","children":null,"spread":false},{"title":"rtl_work","children":[{"title":"_vmake <span style='color:#111;'> 26B </span>","children":null,"spread":false},{"title":"counter_vlg_tst","children":[{"title":"verilog.prw <span style='color:#111;'> 2.63KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 758B </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 90B </span>","children":null,"spread":false},{"title":"verilog.psm <span style='color:#111;'> 9.58KB </span>","children":null,"spread":false},{"title":"_primary.dbs <span style='color:#111;'> 1.16KB </span>","children":null,"spread":false}],"spread":true},{"title":"_temp","children":null,"spread":false},{"title":"counter","children":[{"title":"verilog.prw <span style='color:#111;'> 1.58KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 429B </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 343B </span>","children":null,"spread":false},{"title":"verilog.psm <span style='color:#111;'> 5.28KB </span>","children":null,"spread":false},{"title":"_primary.dbs <span style='color:#111;'> 845B </span>","children":null,"spread":false}],"spread":true},{"title":"_info <span style='color:#111;'> 608B </span>","children":null,"spread":false}],"spread":true},{"title":"msim_transcript <span style='color:#111;'> 2.20KB </span>","children":null,"spread":false},{"title":"counter_run_msim_rtl_verilog.do <span style='color:#111;'> 479B </span>","children":null,"spread":false},{"title":"counter_run_msim_rtl_verilog.do.bak3 <span style='color:#111;'> 479B </span>","children":null,"spread":false},{"title":"vsim.wlf <span style='color:#111;'> 40.00KB </span>","children":null,"spread":false},{"title":"counter_run_msim_rtl_verilog.do.bak1 <span style='color:#111;'> 479B </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"incremental_db","children":[{"title":"compiled_partitions","children":[{"title":"counter.db_info <span style='color:#111;'> 153B </span>","children":null,"spread":false},{"title":"counter.root_partition.map.dpi <span style='color:#111;'> 660B </span>","children":null,"spread":false},{"title":"counter.root_partition.map.cdb <span style='color:#111;'> 2.57KB </span>","children":null,"spread":false},{"title":"counter.root_partition.map.kpt <span style='color:#111;'> 483B </span>","children":null,"spread":false},{"title":"counter.root_partition.map.hdb <span style='color:#111;'> 8.56KB </span>","children":null,"spread":false}],"spread":true},{"title":"README <span style='color:#111;'> 653B </span>","children":null,"spread":false}],"spread":true},{"title":"counter.v <span style='color:#111;'> 408B </span>","children":null,"spread":false},{"title":"counter.eda.rpt <span style='color:#111;'> 2.54KB </span>","children":null,"spread":false},{"title":"counter.map.summary <span style='color:#111;'> 460B </span>","children":null,"spread":false},{"title":"counter.qpf <span style='color:#111;'> 1.25KB </span>","children":null,"spread":false},{"title":"counter_nativelink_simulation.rpt <span style='color:#111;'> 1022B </span>","children":null,"spread":false},{"title":"counter.qsf <span style='color:#111;'> 3.29KB </span>","children":null,"spread":false},{"title":"counter.flow.rpt <span style='color:#111;'> 6.69KB </span>","children":null,"spread":false}],"spread":true}]
评论信息
其他资源
- 掌讯3560-杜比音效+蝰蛇音效-增量单刷包（内有说明）.7z
- RS编码verilog代码与参考文章
- Mayr电弧模型
- linux c 通过http 协议 ，上传文件到服务器 源码
- ADS_CST联合仿真
- 三相pwm整流器仿真
- 同义词词林（当前最全的）
- TVS管的选型方法
- Python金融大数据分析，带目录
- Qt实现托盘全部常用功能示例
- java base64的jar包
- 融合空间模糊C-均值聚类的纱线疵点检测算法
- Java Web项目开发案例精粹14新闻发布系统源码.rar-Java其他资源
- QtChecks.zip
- win7 x32 网卡驱动纯净版
- Android经典游戏：坦克大战
- 同步电机模型的MATLAB仿真
- The LaTeX Graphics Companion英文版
- 套利指标当前双货币差价
- Foundation HTML5 Animation with Javascript (2012)
- 最全的京东商城模板(含所有源代码).rar
免责申明
【只为小站】的资源来自网友分享，仅供学习研究，请务必在下载后24小时内给予删除，不得用于其他任何用途，否则后果自负。基于互联网的特殊性，【只为小站】 无法对用户传输的作品、信息、内容的权属或合法性、合规性、真实性、科学性、完整权、有效性等进行实质审查；无论 【只为小站】 经营者是否已进行审查，用户均应自行承担因其传输的作品、信息、内容而可能或已经产生的侵权或权属纠纷等法律责任。
本站所有资源不代表本站的观点或立场，基于网友分享，根据中国法律《信息网络传播权保护条例》第二十二条之规定，若资源存在侵权或相关问题请联系本站客服人员，zhiweidada#qq.com，请把#换成@，本站将给予最大的支持与配合，做到及时反馈和处理。关于更多版权及免责申明参见 版权及免责申明
本站所有资源不代表本站的观点或立场，基于网友分享，根据中国法律《信息网络传播权保护条例》第二十二条之规定，若资源存在侵权或相关问题请联系本站客服人员，zhiweidada#qq.com，请把#换成@，本站将给予最大的支持与配合，做到及时反馈和处理。关于更多版权及免责申明参见 版权及免责申明