FPGA与上位机的UDP通信.zip

[{"title":"（ 16 个子文件 25KB ） FPGA与上位机的UDP通信.zip","children":[{"title":"DataGetProcessProject","children":[{"title":"udpsrc","children":[{"title":"ram_bb.v <span style='color:#111;'> 7.70KB </span>","children":null,"spread":false},{"title":"iprecieve.v.bak <span style='color:#111;'> 6.22KB </span>","children":null,"spread":false},{"title":"ram.v.bak <span style='color:#111;'> 9.34KB </span>","children":null,"spread":false},{"title":"udp.v <span style='color:#111;'> 3.20KB </span>","children":null,"spread":false},{"title":"ipsend.v <span style='color:#111;'> 7.82KB </span>","children":null,"spread":false},{"title":"ram.v <span style='color:#111;'> 9.34KB </span>","children":null,"spread":false},{"title":"iprecieve.v <span style='color:#111;'> 6.34KB </span>","children":null,"spread":false},{"title":"greybox_tmp","children":[{"title":"cbx_args.txt <span style='color:#111;'> 526B </span>","children":null,"spread":false}],"spread":true},{"title":"Ethernet.v.bak <span style='color:#111;'> 4.13KB </span>","children":null,"spread":false},{"title":"ipsend.v.bak <span style='color:#111;'> 7.22KB </span>","children":null,"spread":false},{"title":"crc.v <span style='color:#111;'> 3.58KB </span>","children":null,"spread":false},{"title":"udp.v.bak <span style='color:#111;'> 2.43KB </span>","children":null,"spread":false},{"title":"crc.v.bak <span style='color:#111;'> 3.58KB </span>","children":null,"spread":false},{"title":"Ethernet.v <span style='color:#111;'> 8.77KB </span>","children":null,"spread":false},{"title":"ram.qip <span style='color:#111;'> 274B </span>","children":null,"spread":false}],"spread":false},{"title":"pythonsrc","children":[{"title":"window.py <span style='color:#111;'> 2.77KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true}]