基于FPGA用Verilog HDL语言实现的多功能数字钟

上传者: rushierer | 上传时间: 2019-12-21 21:01:12 | 文件大小: 1.07MB | 文件类型: rar
这是一个基于FPGA,用Verilog HDL语言实现的多功能数字钟,课程设计的项目。

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