西南交通大学:计组实验课程设计(源文件)

上传者: 61814350 | 上传时间: 2024-06-18 11:59:45 | 文件大小: 3.14MB | 文件类型: RAR
一. 实验目的:通过学习简单的指令系统及其各指令的操作流程,用 Verilog HDL 语言实 现简单的处理器模块,并通过调用存储器模块,将处理器模块和存储器模块连接形成简 化的计算机核心部件组成的系统。 二. 实验内容 1. 底层用 Verilog HDL 语言实现简单的处理器模块设计。 2. 调用存储器模块设计 64×8 的存储器模块。 3. 顶层用原理图方式将简单的处理器模块和存储器模块连接形成简单的计算机核心 部件组成的系统。 4. 将指令序列存入存储器,然后分析指令执行流程。

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