EDA十二进制程序设计.doc

十二进制计数器 仿真时序图 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity count12 is port(clk,clr,en:in std_logic; q0,q1,q2,q3:out std_logic); end count12; architecture rtl of count12 is signal tem:std_logic_vector(3 downto 0); begin q0<=tem(0); q1<=tem(1); q2<=tem(2); q3<=tem(3); process(clk) begin if(clr='1')then tem<="0000"; elsif(clk'event and clk='1')then if(en='1')then if(tem="1011")then tem<="0000"; else tem<=tem+1; end if; end if; end if; end process; end rtl; 时序图