DCT的verilog实现

[{"title":"（ 11 个子文件 34KB ） DCT的verilog实现","children":[{"title":"verilog dct","children":[{"title":"top1.rar <span style='color:#111;'> 1.29KB </span>","children":null,"spread":false},{"title":"dct","children":[{"title":"fdct.v <span style='color:#111;'> 9.52KB </span>","children":null,"spread":false},{"title":"dctu.v <span style='color:#111;'> 245.37KB </span>","children":null,"spread":false},{"title":"dctub.v <span style='color:#111;'> 4.58KB </span>","children":null,"spread":false},{"title":"zigzag.v <span style='color:#111;'> 7.62KB </span>","children":null,"spread":false},{"title":"dct.v <span style='color:#111;'> 9.10KB </span>","children":null,"spread":false},{"title":"dct_syn.v <span style='color:#111;'> 3.81KB </span>","children":null,"spread":false},{"title":"ro_cnt.v <span style='color:#111;'> 3.83KB </span>","children":null,"spread":false},{"title":"ud_cnt.v <span style='color:#111;'> 3.85KB </span>","children":null,"spread":false},{"title":"dct_mac.v <span style='color:#111;'> 4.35KB </span>","children":null,"spread":false}],"spread":true},{"title":"top1.v <span style='color:#111;'> 4.62KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]