[{"title":"( 4 个子文件 2KB ) 乘法器的Verilog实现","children":[{"title":"MULTU","children":[{"title":"MULTU.v <span style='color:#111;'> 1.10KB </span>","children":null,"spread":false},{"title":"MULTU_tb.v <span style='color:#111;'> 1.45KB </span>","children":null,"spread":false}],"spread":true},{"title":"MULT","children":[{"title":"MULT.v <span style='color:#111;'> 1.52KB </span>","children":null,"spread":false},{"title":"MULT_tb.v <span style='color:#111;'> 1.39KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]