qpsk调制解调fpga实现的非常完整工程，Verilog语言编写

[{"title":"（ 858 个子文件 12.86MB ） qpsk调制解调fpga实现的非常完整工程，Verilog语言编写","children":[{"title":"cic_downsample_16_cic.vhd <span style='color:#111;'> 16.13KB </span>","children":null,"spread":false},{"title":"fir_downsample_1.html <span style='color:#111;'> 6.11KB </span>","children":null,"spread":false},{"title":"fir_downsample_1_model.m <span style='color:#111;'> 4.74KB </span>","children":null,"spread":false},{"title":"pulse_shaping_filter_model.m <span style='color:#111;'> 4.56KB </span>","children":null,"spread":false},{"title":"fir_downsample_16_coef_1.hex <span style='color:#111;'> 381B </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]