基于fpga的38译码器的设计
译码器设计
一、实验目的:
1、通过3-8译码器的设计，让学生掌握组合逻辑电路的设计方法。
2、掌握组合逻辑电路的静态测试方法。
3、初步了解可编程器件设计的全过程。
二、实验要求:
1、采用原理图输入设计。
2、采用quartusii自带仿真工具进行波形仿真。
3、连线并下载程序到实验平台，进行硬件验证。
三、实验原理:
3-8译码器工作原理如下:
当一个选通端(G1) 为高电平，另两个选通端((G2A)和/(G2B) 为低电平时，可将地址端(A、B、C)的二进制编码在一个对应的输出端以低电平译出。
3-8译码器的作用:
利用G1、 /(G2A)和/(G2B)可级联扩展成24线译码器;若外接-一个 反相器还可级联扩展成32线译码器。若将选通端中的一个作为数据输入端时，74LS138 还可作数据分配器。
四、实验过程及结果
1.根据译码器的原理，设计原理图，在quartus ii中画出原理图;
2.对原理图进行编译;
3.利用quartusii 自带的仿真软件进行仿真;
文件下载
资源详情
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