[{"title":"( 6 个子文件 106.14MB ) Verilog HDL.zip","children":[{"title":"硬件描述语言Verilog(第3章).pdf <span style='color:#111;'> 7.51MB </span>","children":null,"spread":false},{"title":"硬件描述语言Verilog(第4章).pdf <span style='color:#111;'> 17.54MB </span>","children":null,"spread":false},{"title":"硬件描述语言Verilog(第1,2章).pdf <span style='color:#111;'> 6.34MB </span>","children":null,"spread":false},{"title":"硬件描述语言Verilog(第6章).pdf <span style='color:#111;'> 18.03MB </span>","children":null,"spread":false},{"title":"硬件描述语言Verilog(第5章).pdf <span style='color:#111;'> 44.45MB </span>","children":null,"spread":false},{"title":"硬件描述语言Verilog(第7章).pdf <span style='color:#111;'> 20.01MB </span>","children":null,"spread":false}],"spread":true}]