[{"title":"( 356 个子文件 1.75MB ) UART IP核(verilog代码及说明文档)","children":[{"title":"index.shtml <span style='color:#111;'> 1.26KB </span>","children":null,"spread":false},{"title":"timescale.v <span style='color:#111;'> 4.27KB </span>","children":null,"spread":false},{"title":"uart_defines.v <span style='color:#111;'> 9.36KB </span>","children":null,"spread":false},{"title":"uart_fifo.v <span style='color:#111;'> 9.79KB </span>","children":null,"spread":false},{"title":"uart_wb.v <span style='color:#111;'> 10.21KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多,未全部展示</span>","children":null,"spread":false}],"spread":true}]