可编程硬件描述语言VHDL Quartus moore状态机源代码.pdf

VHDL Quartus Moore状态机源代码 --Moore状态机输出只依赖于器件的当前状态，与输入信号无关 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; --------------------------------------------- ENTITY MOORE IS PORT ( RST: IN STD_LOGIC;--复位功能 CLK: IN STD_LOGIC;--时钟输入 X: IN STD_LOGIC;--输入 OP: OUT STD_LOGIC--输出 ); END ENTITY MOORE; ---------------------------------------------- ARCHITECTURE A OF MOORE IS