上传者: 27595745
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上传时间: 2021-08-21 09:38:03
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文件大小: 162KB
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文件类型: PDF
VHDL Quartus 四分频器源代码
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
----------------------------------------------
ENTITY clk_div IS
PORT(
clk: IN STD_LOGIC;--时钟输入
clk_div2: OUT STD_LOGIC;
clk_div4: OUT STD_LOGIC;
clk_div8: OUT STD_LOGIC;
clk_div16: OUT STD_LOGIC
);
END ENTITY clk_div;
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ARCHITECTURE rtl OF clk_div IS