元件例化16位全加器（Verilog）

[{"title":"（ 161 个子文件 2.93MB ） 元件例化16位全加器（Verilog）","children":[{"title":"rca_16_tb.v <span style='color:#111;'> 391B </span>","children":null,"spread":false},{"title":"project04_nativelink_simulation.rpt <span style='color:#111;'> 990B </span>","children":null,"spread":false},{"title":"add_rca_tb.v <span style='color:#111;'> 382B </span>","children":null,"spread":false},{"title":"project04.cmp.idb <span style='color:#111;'> 3.30KB </span>","children":null,"spread":false},{"title":"project04.db_info <span style='color:#111;'> 140B </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]