[{"title":"( 228 个子文件 454KB ) Verilog 简单练习源代码","children":[{"title":"half_clk.pin <span style='color:#111;'> 38.78KB </span>","children":null,"spread":false},{"title":"half_clock.bdf <span style='color:#111;'> 3.24KB </span>","children":null,"spread":false},{"title":"half_clk.qpf <span style='color:#111;'> 908B </span>","children":null,"spread":false},{"title":"half_clk.fit.smsg <span style='color:#111;'> 334B </span>","children":null,"spread":false},{"title":"half_clk.tan.rpt <span style='color:#111;'> 15.86KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多,未全部展示</span>","children":null,"spread":false}],"spread":true}]