[{"title":"( 101 个子文件 316KB ) 基于quartus II 设计的全加器VHDL,逻辑图以及VWF","children":[{"title":"FA.asm.rpt <span style='color:#111;'> 7.25KB </span>","children":null,"spread":false},{"title":"FA.done <span style='color:#111;'> 26B </span>","children":null,"spread":false},{"title":"FA.tan.summary <span style='color:#111;'> 705B </span>","children":null,"spread":false},{"title":"FA.qsf <span style='color:#111;'> 2.68KB </span>","children":null,"spread":false},{"title":"FA.pof <span style='color:#111;'> 2.00MB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多,未全部展示</span>","children":null,"spread":false}],"spread":true}]