[{"title":"( 24 个子文件 17.8MB ) Testbench超全教程","children":[{"title":"Testbench教程","children":[{"title":"英文文章:testbench入门文档(xilinx的).pdf <span style='color:#111;'> 274.69KB </span>","children":null,"spread":false},{"title":"Xilinx—Writing Efficient Testbenches.pdf <span style='color:#111;'> 274.69KB </span>","children":null,"spread":false},{"title":"在QUARTUS下根据波形文件生成testbench.doc <span style='color:#111;'> 23.50KB </span>","children":null,"spread":false},{"title":"Writing Testbenches using SystemVerilog.pdf <span style='color:#111;'> 2.02MB </span>","children":null,"spread":false},{"title":"计数器程序与TESTBENCH.doc <span style='color:#111;'> 23.00KB </span>","children":null,"spread":false},{"title":"怎样写test bench..pdf <span style='color:#111;'> 100.30KB </span>","children":null,"spread":false},{"title":"学写 Testbench --- 结构篇.doc <span style='color:#111;'> 34.50KB </span>","children":null,"spread":false},{"title":"test bench.ppt <span style='color:#111;'> 128.00KB </span>","children":null,"spread":false},{"title":"编写高效的测试设计(testbenches).doc <span style='color:#111;'> 421.50KB </span>","children":null,"spread":false},{"title":"中文文章:怎样写testbench(xilinx的).pdf <span style='color:#111;'> 100.30KB </span>","children":null,"spread":false},{"title":"一些好的关于testbench资料","children":[{"title":"testbench_book.pdf <span style='color:#111;'> 2.03MB </span>","children":null,"spread":false},{"title":"如何编写testbench的总结.pdf <span style='color:#111;'> 247.32KB </span>","children":null,"spread":false},{"title":"TestBench的书写.ppt <span style='color:#111;'> 174.50KB </span>","children":null,"spread":false},{"title":"怎样写testbench.pdf <span style='color:#111;'> 100.30KB </span>","children":null,"spread":false},{"title":"Writing Test Benches.pdf <span style='color:#111;'> 1.04MB </span>","children":null,"spread":false},{"title":"An Overview on Writing a VHDL Testbench.pdf <span style='color:#111;'> 397.64KB </span>","children":null,"spread":false},{"title":"Writing Efficient Testbenches.pdf <span style='color:#111;'> 274.69KB </span>","children":null,"spread":false},{"title":"verilog testbench preliminary.pdf <span style='color:#111;'> 85.72KB </span>","children":null,"spread":false},{"title":"testbench_vantage.pdf <span style='color:#111;'> 51.08KB </span>","children":null,"spread":false},{"title":"writing testbench.pdf <span style='color:#111;'> 1.22MB </span>","children":null,"spread":false},{"title":"书写testbench过程.doc <span style='color:#111;'> 67.50KB </span>","children":null,"spread":false},{"title":"A Verilog HDL Test Bench Primer.pdf <span style='color:#111;'> 63.94KB </span>","children":null,"spread":false}],"spread":false},{"title":"Test Bench 经典教程.pdf <span style='color:#111;'> 63.94KB </span>","children":null,"spread":false},{"title":"怎样用VHDL写TESTBENCH.pdf <span style='color:#111;'> 13.79MB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]