单端口RAM的VHDL实现

[{"title":"（ 12 个子文件 39KB ） 单端口RAM的VHDL实现","children":[{"title":"nut_spram","children":[{"title":"par","children":null,"spread":false},{"title":"rtl","children":[{"title":"nut_spram_rw.vhd <span style='color:#111;'> 2.12KB </span>","children":null,"spread":false},{"title":"nut_spram.vhd <span style='color:#111;'> 804B </span>","children":null,"spread":false}],"spread":true},{"title":"sim","children":[{"title":"vhdl","children":[{"title":"nut_spram_tb.vhd <span style='color:#111;'> 1.01KB </span>","children":null,"spread":false}],"spread":true},{"title":"vsim.wlf <span style='color:#111;'> 56.00KB </span>","children":null,"spread":false},{"title":"work","children":[{"title":"_lib.qdb <span style='color:#111;'> 48.00KB </span>","children":null,"spread":false},{"title":"_lib1_7.qdb <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false},{"title":"_lib1_7.qpg <span style='color:#111;'> 32.00KB </span>","children":null,"spread":false},{"title":"_lib1_7.qtl <span style='color:#111;'> 49.23KB </span>","children":null,"spread":false},{"title":"_info <span style='color:#111;'> 2.45KB </span>","children":null,"spread":false},{"title":"_vmake <span style='color:#111;'> 29B </span>","children":null,"spread":false}],"spread":true},{"title":"nut_spram.cr.mti <span style='color:#111;'> 1.60KB </span>","children":null,"spread":false},{"title":"nut_spram.mpf <span style='color:#111;'> 18.68KB </span>","children":null,"spread":false}],"spread":true},{"title":"doc","children":null,"spread":false}],"spread":true}],"spread":true}]