[{"title":"( 7 个子文件 14KB ) VHDL Uart 源码","children":[{"title":"VHDL_UART","children":[{"title":"Rxcver.vhd <span style='color:#111;'> 10.49KB </span>","children":null,"spread":false},{"title":"scibd.vhd <span style='color:#111;'> 2.13KB </span>","children":null,"spread":false},{"title":"Intface.vhd <span style='color:#111;'> 13.58KB </span>","children":null,"spread":false},{"title":"Scitop.vhd <span style='color:#111;'> 12.08KB </span>","children":null,"spread":false},{"title":"loopback.vhd <span style='color:#111;'> 646B </span>","children":null,"spread":false},{"title":"Txmitt.vhd <span style='color:#111;'> 7.93KB </span>","children":null,"spread":false},{"title":"Modem.vhd <span style='color:#111;'> 2.22KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]