(精选)FPGA项目沙盘演练-基础版报文收发(vivado2017.4)

上传者: m0_52840978 | 上传时间: 2024-07-04 15:30:25 | 文件大小: 31.18MB | 文件类型: ZIP
(详细项目内容请看对应博客正文,本资源为对应项目工程,含仿真文件) 一、项目要求 1.输入报文长度64~2048字节; 2.输入报文之间最小间隔为两拍; 3.输出报文的前两拍添加16bit报文长度信息;第1拍为报文长度高8位;第2拍为报文长度低8位;第3拍开始为输入报文; 二、项目方案 1. 要求输出报文,且报文输出在报文长度输出之后,所以需要先对输入报文进行缓存,根据输入报文的位宽和长度范围,此处选择合适的同步FIFO即可;(如果是IC,那么就需要自己写FIFO,可以参考本博客的FIFO介绍) 这里项目提出了第1个要求,掌握FIFO的使用。 2. 要求输出报文长度,所以需要对输入报文长度进行计数,并将其缓存; 此处有坑,若只用寄存器对长度进行缓存,存在被后续报文长度覆盖的风险,故需要第2个FIFO对报文长度进行缓存。 3. 要求先输出报文长度然后紧跟着输出报文,此处需要对时序进行设计,需要掌握FIFO的读写时序,需要理解fpga的时钟沿采样。 理解:时钟沿采样及数据下一时钟沿变化。

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