FPGA等精度测频法 ISE下verilog实现

[{"title":"（ 133 个子文件 1.47MB ） FPGA等精度测频法 ISE下verilog实现","children":[{"title":"pregate_guide.ncd <span style='color:#111;'> 47.69KB </span>","children":null,"spread":false},{"title":"webtalk.log <span style='color:#111;'> 680B </span>","children":null,"spread":false},{"title":"isim.log <span style='color:#111;'> 444B </span>","children":null,"spread":false},{"title":"pregate_summary.html <span style='color:#111;'> 9.07KB </span>","children":null,"spread":false},{"title":"webtalk_pn.xml <span style='color:#111;'> 2.95KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]