数字时钟Verilog

[{"title":"（ 128 个子文件 507KB ） 数字时钟Verilog","children":[{"title":"counter60.bin <span style='color:#111;'> 7.01KB </span>","children":null,"spread":false},{"title":"_x___e_n.bin <span style='color:#111;'> 3.34KB </span>","children":null,"spread":false},{"title":"counter24.bin <span style='color:#111;'> 5.77KB </span>","children":null,"spread":false},{"title":"_divider50_m__to__x_h_z.bin <span style='color:#111;'> 4.39KB </span>","children":null,"spread":false},{"title":"_display.bin <span style='color:#111;'> 2.72KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]