Verilog设计3-8译码器、8位全加器、四分之一分频器.zip

[{"title":"（ 6 个子文件 4KB ） Verilog设计3-8译码器、8位全加器、四分之一分频器.zip","children":[{"title":"Verilog设计3-8译码器、8位全加器、四分之一分频器","children":[{"title":"divider","children":[{"title":"divider_t.v <span style='color:#111;'> 406B </span>","children":null,"spread":false},{"title":"divider.v <span style='color:#111;'> 467B </span>","children":null,"spread":false}],"spread":true},{"title":"adder","children":[{"title":"adder.v <span style='color:#111;'> 201B </span>","children":null,"spread":false},{"title":"adder_t.v <span style='color:#111;'> 704B </span>","children":null,"spread":false}],"spread":true},{"title":"decoder","children":[{"title":"decoder_t.v <span style='color:#111;'> 455B </span>","children":null,"spread":false},{"title":"decoder.v <span style='color:#111;'> 538B </span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true}]