通过 UART 读写 SDRAM verilog 源代码, 附时序约束文件

[{"title":"（ 12 个子文件 14KB ） 通过 UART 读写 SDRAM verilog 源代码, 附时序约束文件","children":[{"title":"uart_recv.v <span style='color:#111;'> 1.95KB </span>","children":null,"spread":false},{"title":"uart_clk.v <span style='color:#111;'> 658B </span>","children":null,"spread":false},{"title":"uart_send.v <span style='color:#111;'> 1.80KB </span>","children":null,"spread":false},{"title":"sys_ctrl.v <span style='color:#111;'> 2.07KB </span>","children":null,"spread":false},{"title":"pll_ctrl_syn.v <span style='color:#111;'> 7.25KB </span>","children":null,"spread":false},{"title":"sdr_test_top.sdc <span style='color:#111;'> 14.21KB </span>","children":null,"spread":false},{"title":"sdr_param.v <span style='color:#111;'> 1.42KB </span>","children":null,"spread":false},{"title":"pll_ctrl_bb.v <span style='color:#111;'> 12.31KB </span>","children":null,"spread":false},{"title":"sdr_ctrl.v <span style='color:#111;'> 8.79KB </span>","children":null,"spread":false},{"title":"pll_ctrl.v <span style='color:#111;'> 16.21KB </span>","children":null,"spread":false},{"title":"sdr_test_top.v <span style='color:#111;'> 1.93KB </span>","children":null,"spread":false},{"title":"uio_ctrl.v <span style='color:#111;'> 5.08KB </span>","children":null,"spread":false}],"spread":true}]