[{"title":"( 4 个子文件 2.22MB ) Altera 官方SDRAM_controller IP CORE源代码","children":[{"title":"Altera 官方SDRAM_controller IP CORE","children":[{"title":"vhdl.rar <span style='color:#111;'> 936.25KB </span>","children":null,"spread":false},{"title":"使用说明请参看右侧注释====〉〉.txt <span style='color:#111;'> 774B </span>","children":null,"spread":false},{"title":"verilog.rar <span style='color:#111;'> 759.18KB </span>","children":null,"spread":false},{"title":"sdr_sdram.rar <span style='color:#111;'> 608.39KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]