8051IP核Verilog和VHDL代码全集.A

上传者: leopold_2008 | 上传时间: 2020-01-03 11:24:33 | 文件大小: 247KB | 文件类型: rar
8051IP核Verilog和VHDL代码全集.A:8051核(Verilog版)::反向解剖是学习IC设计的捷径,希望对大家有帮助!

文件下载

资源详情

[{"title":"( 61 个子文件 247KB ) 8051IP核Verilog和VHDL代码全集.A","children":[{"title":"8051的Verilog源代码","children":[{"title":"bench","children":[{"title":"verilog","children":[{"title":"oc8051_fpga_tb.v <span style='color:#111;'> 1.18KB </span>","children":null,"spread":false},{"title":"oc8051_defines.v <span style='color:#111;'> 15.75KB </span>","children":null,"spread":false},{"title":"oc8051_tb.v <span style='color:#111;'> 4.12KB </span>","children":null,"spread":false},{"title":"oc8051_timescale.v <span style='color:#111;'> 22B </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"syn","children":[{"title":"out","children":[{"title":"oc8051_top.bit <span style='color:#111;'> 575.71KB </span>","children":null,"spread":false},{"title":"oc8051_top.srm <span style='color:#111;'> 442.65KB </span>","children":null,"spread":false},{"title":"oc8051_top.srs <span style='color:#111;'> 165.66KB </span>","children":null,"spread":false},{"title":"oc8051.ucf <span style='color:#111;'> 866B </span>","children":null,"spread":false},{"title":"read.me <span style='color:#111;'> 98B </span>","children":null,"spread":false}],"spread":true},{"title":"log","children":[{"title":"oc8051_top.srr <span style='color:#111;'> 43.13KB </span>","children":null,"spread":false}],"spread":true},{"title":"src","children":[{"title":"verilog","children":[{"title":"oc8051_ram.v <span style='color:#111;'> 3.89KB </span>","children":null,"spread":false},{"title":"oc8051_fpga_top.v <span style='color:#111;'> 4.61KB </span>","children":null,"spread":false},{"title":"disp.v <span style='color:#111;'> 1.37KB </span>","children":null,"spread":false},{"title":"oc8051_rom.v <span style='color:#111;'> 7.53KB </span>","children":null,"spread":false},{"title":"read me.txt <span style='color:#111;'> 51B </span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true},{"title":"8051_rtl","children":[{"title":"verilog","children":[{"title":"oc8051_reg4.v <span style='color:#111;'> 3.21KB </span>","children":null,"spread":false},{"title":"oc8051_fpga_tb.v <span style='color:#111;'> 1.18KB </span>","children":null,"spread":false},{"title":"oc8051_reg1.v <span style='color:#111;'> 3.19KB </span>","children":null,"spread":false},{"title":"oc8051_alu_src2_sel.v <span style='color:#111;'> 3.57KB </span>","children":null,"spread":false},{"title":"oc8051_reg3.v <span style='color:#111;'> 3.21KB </span>","children":null,"spread":false},{"title":"oc8051_top.v <span style='color:#111;'> 13.44KB </span>","children":null,"spread":false},{"title":"oc8051_defines.v <span style='color:#111;'> 15.75KB </span>","children":null,"spread":false},{"title":"oc8051_fpga_top.v <span style='color:#111;'> 1.63KB </span>","children":null,"spread":false},{"title":"oc8051_port_out.v <span style='color:#111;'> 4.39KB </span>","children":null,"spread":false},{"title":"oc8051_multiply.v <span style='color:#111;'> 2.39KB </span>","children":null,"spread":false},{"title":"oc8051_sp.v <span style='color:#111;'> 5.18KB </span>","children":null,"spread":false},{"title":"oc8051_dptr.v <span style='color:#111;'> 4.07KB </span>","children":null,"spread":false},{"title":"oc8051_divide.v <span style='color:#111;'> 4.66KB </span>","children":null,"spread":false},{"title":"oc8051_ext_addr_sel.v <span style='color:#111;'> 3.60KB </span>","children":null,"spread":false},{"title":"oc8051_alu_src1_sel.v <span style='color:#111;'> 3.74KB </span>","children":null,"spread":false},{"title":"oc8051_reg2.v <span style='color:#111;'> 3.21KB </span>","children":null,"spread":false},{"title":"oc8051_ram_sel1.v <span style='color:#111;'> 4.63KB </span>","children":null,"spread":false},{"title":"oc8051_psw.v <span style='color:#111;'> 5.00KB </span>","children":null,"spread":false},{"title":"oc8051_ram_rd_sel.v <span style='color:#111;'> 3.65KB </span>","children":null,"spread":false},{"title":"oc8051_decoder.v <span style='color:#111;'> 98.64KB </span>","children":null,"spread":false},{"title":"oc8051_op_select.v <span style='color:#111;'> 5.73KB </span>","children":null,"spread":false},{"title":"oc8051_ram_sel.v <span style='color:#111;'> 4.70KB </span>","children":null,"spread":false},{"title":"oc8051_reg5.v <span style='color:#111;'> 3.21KB </span>","children":null,"spread":false},{"title":"oc8051_comp.v <span style='color:#111;'> 3.83KB </span>","children":null,"spread":false},{"title":"oc8051_ram_top.v <span style='color:#111;'> 6.87KB </span>","children":null,"spread":false},{"title":"oc8051_rom_addr_sel.v <span style='color:#111;'> 3.90KB </span>","children":null,"spread":false},{"title":"oc8051_pc.v <span style='color:#111;'> 8.40KB </span>","children":null,"spread":false},{"title":"oc8051_cy_select.v <span style='color:#111;'> 3.60KB </span>","children":null,"spread":false},{"title":"oc8051_tb.v <span style='color:#111;'> 4.18KB </span>","children":null,"spread":false},{"title":"oc8051_acc.v <span style='color:#111;'> 4.35KB </span>","children":null,"spread":false},{"title":"oc8051_ram_wr_sel.v <span style='color:#111;'> 3.84KB </span>","children":null,"spread":false},{"title":"oc8051_alu.v <span style='color:#111;'> 7.43KB </span>","children":null,"spread":false},{"title":"oc8051_top1.v <span style='color:#111;'> 13.01KB </span>","children":null,"spread":false},{"title":"oc8051_alu_src3_sel.v <span style='color:#111;'> 3.32KB </span>","children":null,"spread":false},{"title":"oc8051_reg8.v <span style='color:#111;'> 3.26KB </span>","children":null,"spread":false},{"title":"oc8051_timescale.v <span style='color:#111;'> 22B </span>","children":null,"spread":false},{"title":"oc8051_immediate_sel.v <span style='color:#111;'> 3.66KB </span>","children":null,"spread":false},{"title":"oc8051_ram_top1.v <span style='color:#111;'> 6.85KB </span>","children":null,"spread":false},{"title":"read me.txt <span style='color:#111;'> 95B </span>","children":null,"spread":false},{"title":"oc8051_indi_addr.v <span style='color:#111;'> 4.70KB </span>","children":null,"spread":false}],"spread":false}],"spread":true},{"title":"sim","children":[{"title":"rtl_sim","children":[{"title":"out","children":[{"title":"VERILOG.LOG <span style='color:#111;'> 18.54KB </span>","children":null,"spread":false}],"spread":true},{"title":"src","children":[{"title":"verilog","children":[{"title":"oc8051_ram.v <span style='color:#111;'> 3.75KB </span>","children":null,"spread":false},{"title":"oc8051_rom.v <span style='color:#111;'> 6.73KB </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"run","children":[{"title":"make_fpga <span style='color:#111;'> 1.36KB </span>","children":null,"spread":false},{"title":"MAKE <span style='color:#111;'> 1.28KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true},{"title":"asm","children":[{"title":"test.asm <span style='color:#111;'> 945B </span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true}]

评论信息

  • dr11001 :
    代码很好有时间看看,求快速掌握
    2015-08-12
  • 缄默的SJ君 :
    很好很强大!对我很有帮助!
    2014-01-08
  • zh190588 :
    很好,很强大。感觉要是把这个掌握了,应该觉得不错了
    2013-08-09
  • yanghongbin818 :
    代码挺详细,看着不错,有时间试试。
    2013-05-07

免责申明

【只为小站】的资源来自网友分享,仅供学习研究,请务必在下载后24小时内给予删除,不得用于其他任何用途,否则后果自负。基于互联网的特殊性,【只为小站】 无法对用户传输的作品、信息、内容的权属或合法性、合规性、真实性、科学性、完整权、有效性等进行实质审查;无论 【只为小站】 经营者是否已进行审查,用户均应自行承担因其传输的作品、信息、内容而可能或已经产生的侵权或权属纠纷等法律责任。
本站所有资源不代表本站的观点或立场,基于网友分享,根据中国法律《信息网络传播权保护条例》第二十二条之规定,若资源存在侵权或相关问题请联系本站客服人员,zhiweidada#qq.com,请把#换成@,本站将给予最大的支持与配合,做到及时反馈和处理。关于更多版权及免责申明参见 版权及免责申明