[{"title":"( 11 个子文件 8KB ) FPGA串口通信程序(Verilog)","children":[{"title":"bwptr.v <span style='color:#111;'> 1.64KB </span>","children":null,"spread":false},{"title":"comp.v <span style='color:#111;'> 1.11KB </span>","children":null,"spread":false},{"title":"fifo.v <span style='color:#111;'> 1.33KB </span>","children":null,"spread":false},{"title":"uart_top.v <span style='color:#111;'> 1.53KB </span>","children":null,"spread":false},{"title":"send.v <span style='color:#111;'> 2.33KB </span>","children":null,"spread":false},{"title":"fifo_control_tf.v <span style='color:#111;'> 2.17KB </span>","children":null,"spread":false},{"title":"rec.v <span style='color:#111;'> 2.61KB </span>","children":null,"spread":false},{"title":"brptr.v <span style='color:#111;'> 1.64KB </span>","children":null,"spread":false},{"title":"uart_tf.v <span style='color:#111;'> 7.17KB </span>","children":null,"spread":false},{"title":"control_fifo.v <span style='color:#111;'> 2.84KB </span>","children":null,"spread":false},{"title":"fifomen.v <span style='color:#111;'> 1.46KB </span>","children":null,"spread":false}],"spread":true}]