基于vhdl语言设计的ram

[{"title":"（ 65 个子文件 165KB ） 基于vhdl语言设计的ram","children":[{"title":"ram","children":[{"title":"asynram.qpf <span style='color:#111;'> 1.52KB </span>","children":null,"spread":false},{"title":"asynram.vwf <span style='color:#111;'> 16.06KB </span>","children":null,"spread":false},{"title":"asynram.map.eqn <span style='color:#111;'> 13.10KB </span>","children":null,"spread":false},{"title":"asynram.asm.rpt <span style='color:#111;'> 6.84KB </span>","children":null,"spread":false},{"title":"asynram.pof <span style='color:#111;'> 207.14KB </span>","children":null,"spread":false},{"title":"asynram.fit.summary <span style='color:#111;'> 378B </span>","children":null,"spread":false},{"title":"asynram.vhd <span style='color:#111;'> 980B </span>","children":null,"spread":false},{"title":"asynram.fit.rpt <span style='color:#111;'> 39.89KB </span>","children":null,"spread":false},{"title":"db","children":[{"title":"asynram.cmp.cdb <span style='color:#111;'> 11.09KB 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style='color:#111;'> 1.13KB </span>","children":null,"spread":false},{"title":"asynram.fnsim.qmsg <span style='color:#111;'> 6.00KB </span>","children":null,"spread":false},{"title":"asynram.cmp0.ddb <span style='color:#111;'> 5.11KB </span>","children":null,"spread":false},{"title":"asynram.rtlv_sg_swap.cdb <span style='color:#111;'> 158B </span>","children":null,"spread":false},{"title":"asynram.(0).cnf.hdb <span style='color:#111;'> 786B </span>","children":null,"spread":false},{"title":"asynram.syn_hier_info <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"asynram.db_info <span style='color:#111;'> 136B </span>","children":null,"spread":false},{"title":"asynram.sgdiff.hdb <span style='color:#111;'> 7.61KB </span>","children":null,"spread":false},{"title":"asynram.sim.vwf <span style='color:#111;'> 16.93KB </span>","children":null,"spread":false},{"title":"asynram_cmp.qrpt <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"asynram.(0).cnf.cdb <span style='color:#111;'> 1.19KB </span>","children":null,"spread":false},{"title":"asynram.map.qmsg <span style='color:#111;'> 7.06KB </span>","children":null,"spread":false},{"title":"asynram.map.cdb <span style='color:#111;'> 3.68KB </span>","children":null,"spread":false},{"title":"asynram.fit.qmsg <span style='color:#111;'> 4.29KB </span>","children":null,"spread":false},{"title":"asynram.cmp.hdb <span style='color:#111;'> 7.72KB </span>","children":null,"spread":false},{"title":"asynram.rtlv_sg.cdb <span style='color:#111;'> 1.09KB </span>","children":null,"spread":false},{"title":"asynram.cbx.xml <span style='color:#111;'> 89B </span>","children":null,"spread":false},{"title":"asynram.fnsim.hdb <span style='color:#111;'> 7.69KB </span>","children":null,"spread":false},{"title":"asynram.eco.cdb <span style='color:#111;'> 141B </span>","children":null,"spread":false},{"title":"asynram.(1).cnf.hdb <span style='color:#111;'> 954B </span>","children":null,"spread":false},{"title":"asynram.map.hdb <span style='color:#111;'> 6.74KB </span>","children":null,"spread":false},{"title":"asynram.hif <span style='color:#111;'> 3.43KB </span>","children":null,"spread":false},{"title":"asynram.asm.qmsg <span style='color:#111;'> 1.39KB </span>","children":null,"spread":false},{"title":"asynram.psp <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"asynram.sim.hdb <span style='color:#111;'> 2.33KB </span>","children":null,"spread":false},{"title":"asynram.sld_design_entry.sci <span style='color:#111;'> 134B </span>","children":null,"spread":false},{"title":"asynram.hier_info <span style='color:#111;'> 997B </span>","children":null,"spread":false},{"title":"asynram.sld_design_entry_dsc.sci <span style='color:#111;'> 134B </span>","children":null,"spread":false},{"title":"asynram.cmp.qrpt <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"asynram.tan.qmsg <span style='color:#111;'> 36.30KB </span>","children":null,"spread":false},{"title":"asynram.sim.qrpt <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"asynram.(1).cnf.cdb <span style='color:#111;'> 1.26KB </span>","children":null,"spread":false},{"title":"asynram.eds_overflow <span style='color:#111;'> 3B </span>","children":null,"spread":false}],"spread":false},{"title":"asynram.fit.eqn <span style='color:#111;'> 14.32KB </span>","children":null,"spread":false},{"title":"asynram.qsf <span style='color:#111;'> 2.66KB </span>","children":null,"spread":false},{"title":"asynram_assignment_defaults.qdf <span style='color:#111;'> 34.14KB </span>","children":null,"spread":false},{"title":"asynram.pin <span style='color:#111;'> 25.02KB </span>","children":null,"spread":false},{"title":"asynram.map.summary <span style='color:#111;'> 294B </span>","children":null,"spread":false},{"title":"asynram.sof <span style='color:#111;'> 160.35KB </span>","children":null,"spread":false},{"title":"cmp_state.ini <span style='color:#111;'> 2B </span>","children":null,"spread":false},{"title":"asynram.tan.rpt <span style='color:#111;'> 76.82KB </span>","children":null,"spread":false},{"title":"asynram.map.rpt <span style='color:#111;'> 19.20KB </span>","children":null,"spread":false},{"title":"asynram.sim.rpt <span style='color:#111;'> 17.02KB </span>","children":null,"spread":false},{"title":"asynram.tan.summary <span style='color:#111;'> 1.81KB </span>","children":null,"spread":false},{"title":"asynram.qws <span style='color:#111;'> 1.23KB </span>","children":null,"spread":false},{"title":"asynram.done <span style='color:#111;'> 26B </span>","children":null,"spread":false},{"title":"asynram.flow.rpt <span style='color:#111;'> 3.42KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]