LCD1602屏 (EP4CE30) FPGA读写实验Verilog逻辑源码Quartus工程文件+文档资料.rar
LCD1602屏 (EP4CE30) FPGA读写实验Verilog逻辑源码Quartus工程文件+文档资料。FPGA为CYCLONE4系列中的EP4CE30F23C8. 完整的工程文件，可以做为你的学习设计参考。
module LCD1602_Cnt(input sys_clk, //50M
input sys_rst_n,
output reg lcd_rs, //0:write order; 1:write data
output lcd_rw, //0:write data; 1:read data
output reg lcd_en, //
output reg [7:0] lcd_data);
//--------------------lcd1602 order----------------------------
parameter Mode_Set = 8'h38, //������ʾģʽ��8λ2��5x8����
Cursor_Set = 8'h0c, //��ʾ������겻��ʾ�����겻������˸
Address_Set = 8'h06, //���ֲ����������Զ�����
Clear_Set = 8'h01; //��������긴λ
/****************************LCD1602 Display Data****************************/
wire [7:0] data0,data1; //counter data
wire [7:0] addr; //write address
//---------------------------------1s counter-----------------------------------
reg [25:0] cnt1;
reg [7:0] data_r0,data_r1;
always@(posedge sys_clk or negedge sys_rst_n)
begin
if(!sys_rst_n)
begin
cnt1 <= 1'b0;
data_r0 <= 1'b0;
data_r1 <= 1'b0;
end
else if(cnt1==26'd50000000)
begin
if(data_r0==8'd9)
begin
data_r0 <= 1'b0;
if(data_r1==8'd9)
data_r1 <= 1'b0;
else
data_r1 <= data_r1 + 1'b1;
end
else
data_r0 <= data_r0 + 1'b1;
cnt1 <= 1'b0;
end
else
cnt1 <= cnt1 + 1'b1;
end
assign data0 = 8'h30 + data_r0 ;
assign data1 = 8'h30 + data_r1 ;
//-------------------address------------------
assign addr = 8'h80;
/****************************LCD1602 Driver****************************/
//-----------------------lcd1602 sys_clk_en---------------------
reg
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本站所有资源不代表本站的观点或立场，基于网友分享，根据中国法律《信息网络传播权保护条例》第二十二条之规定，若资源存在侵权或相关问题请联系本站客服人员，zhiweidada#qq.com，请把#换成@，本站将给予最大的支持与配合，做到及时反馈和处理。关于更多版权及免责申明参见 版权及免责申明