sdram verilog

[{"title":"（ 45 个子文件 8.29MB ） sdram verilog","children":[{"title":"sdram_sim_model","children":[{"title":"modelsim","children":[{"title":"pll.do <span style='color:#111;'> 465B </span>","children":null,"spread":false},{"title":"system.do <span style='color:#111;'> 1.00KB </span>","children":null,"spread":false},{"title":"data_gen.do <span style='color:#111;'> 576B </span>","children":null,"spread":false},{"title":"fifo.do <span style='color:#111;'> 732B </span>","children":null,"spread":false}],"spread":true},{"title":"sdram_test.mpf <span style='color:#111;'> 80.41KB </span>","children":null,"spread":false},{"title":"src","children":[{"title":"data_gen","children":[{"title":"datagene.v <span style='color:#111;'> 3.77KB </span>","children":null,"spread":false},{"title":"data_gen_module.v <span style='color:#111;'> 818B </span>","children":null,"spread":false},{"title":"data_gen_module_tb.v <span style='color:#111;'> 658B </span>","children":null,"spread":false},{"title":"datagene.v.bak <span style='color:#111;'> 3.77KB </span>","children":null,"spread":false}],"spread":true},{"title":"sdram","children":[{"title":"sdram_module_tb.v <span style='color:#111;'> 1.29KB </span>","children":null,"spread":false},{"title":"sdram_top.v <span style='color:#111;'> 3.69KB </span>","children":null,"spread":false},{"title":"sdram_ctrl.v <span style='color:#111;'> 11.98KB </span>","children":null,"spread":false},{"title":"sdram_cmd.v <span style='color:#111;'> 4.75KB </span>","children":null,"spread":false},{"title":"sdr_para.v <span style='color:#111;'> 2.93KB </span>","children":null,"spread":false},{"title":"sdram_module.v <span style='color:#111;'> 1.54KB </span>","children":null,"spread":false},{"title":"sdram_wr_data.v <span style='color:#111;'> 2.42KB </span>","children":null,"spread":false},{"title":"sdram_top.v.bak <span style='color:#111;'> 3.88KB </span>","children":null,"spread":false}],"spread":true},{"title":"lib","children":[{"title":"altera_mf.v <span style='color:#111;'> 2.14MB </span>","children":null,"spread":false},{"title":"220model.v <span style='color:#111;'> 233.99KB </span>","children":null,"spread":false}],"spread":true},{"title":"pll","children":[{"title":"pll_module_tb.v <span style='color:#111;'> 437B </span>","children":null,"spread":false},{"title":"pll_module.v <span style='color:#111;'> 453B </span>","children":null,"spread":false},{"title":"sys_ctrl.v <span style='color:#111;'> 2.07KB </span>","children":null,"spread":false},{"title":"clk_ctrl.v <span style='color:#111;'> 17.79KB </span>","children":null,"spread":false}],"spread":true},{"title":"sdfifo","children":[{"title":"sdfifo_ctrl.v <span style='color:#111;'> 2.15KB </span>","children":null,"spread":false},{"title":"wrfifo.v <span style='color:#111;'> 6.62KB </span>","children":null,"spread":false},{"title":"rdfifo.v <span style='color:#111;'> 6.62KB </span>","children":null,"spread":false}],"spread":true},{"title":"fifo","children":[{"title":"fifo_test_module.v <span style='color:#111;'> 1.27KB </span>","children":null,"spread":false},{"title":"EasyCapture3.jpg <span style='color:#111;'> 101.24KB </span>","children":null,"spread":false},{"title":"fifo_test_module_tb.v <span style='color:#111;'> 953B </span>","children":null,"spread":false},{"title":"wrfifo.v <span style='color:#111;'> 6.62KB </span>","children":null,"spread":false},{"title":"EasyCapture4.jpg <span style='color:#111;'> 51.04KB </span>","children":null,"spread":false},{"title":"EasyCapture2.jpg <span style='color:#111;'> 73.27KB </span>","children":null,"spread":false},{"title":"EasyCapture5.jpg <span style='color:#111;'> 70.93KB </span>","children":null,"spread":false},{"title":"FIFO模块仿真说明.txt <span style='color:#111;'> 785B </span>","children":null,"spread":false},{"title":"rdfifo.v <span style='color:#111;'> 6.62KB </span>","children":null,"spread":false},{"title":"EasyCapture1.jpg <span style='color:#111;'> 100.84KB </span>","children":null,"spread":false},{"title":"write_fifo_module.v <span style='color:#111;'> 689B </span>","children":null,"spread":false}],"spread":false},{"title":"system","children":[{"title":"system_module_tb.v.bak <span style='color:#111;'> 1.57KB </span>","children":null,"spread":false},{"title":"system_module_tb.v <span style='color:#111;'> 1.57KB </span>","children":null,"spread":false},{"title":"system_module.v.bak <span style='color:#111;'> 2.64KB </span>","children":null,"spread":false},{"title":"system_module.v <span style='color:#111;'> 2.65KB </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"sdram_test.cr.mti <span style='color:#111;'> 8.17KB </span>","children":null,"spread":false},{"title":"vsim.wlf <span style='color:#111;'> 4.36MB </span>","children":null,"spread":false},{"title":"sdram_test.zip <span style='color:#111;'> 4.18MB </span>","children":null,"spread":false},{"title":"wave","children":[{"title":"wave.do <span style='color:#111;'> 2.68KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true}]