FPGA 使用verilog 编写的AD tlc549 测试程序，数码管做显示，本程序已验证

[{"title":"（ 161 个子文件 1.02MB ） FPGA 使用verilog 编写的AD tlc549 测试程序，数码管做显示，本程序已验证","children":[{"title":"column_scan_module.v <span style='color:#111;'> 886B </span>","children":null,"spread":false},{"title":"cbx_args.txt <span style='color:#111;'> 1.41KB </span>","children":null,"spread":false},{"title":"experiment_ram.pin <span style='color:#111;'> 26.48KB </span>","children":null,"spread":false},{"title":"ad_tlc549.v <span style='color:#111;'> 3.40KB </span>","children":null,"spread":false},{"title":"experiment_ram.flow.rpt <span style='color:#111;'> 7.40KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]