基于FPGA的2FSK调制器的实现

[{"title":"（ 46 个子文件 4.41MB ） 基于FPGA的2FSK调制器的实现","children":[{"title":"FSK2","children":[{"title":"FSK2.v.bak <span style='color:#111;'> 1.85KB </span>","children":null,"spread":false},{"title":"FSK2_TP.v <span style='color:#111;'> 578B </span>","children":null,"spread":false},{"title":"work","children":[{"title":"_vmake <span style='color:#111;'> 26B </span>","children":null,"spread":false},{"title":"address","children":[{"title":"_primary.dat <span style='color:#111;'> 295B </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 195B </span>","children":null,"spread":false},{"title":"verilog.rw <span style='color:#111;'> 196B </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 2.53KB </span>","children":null,"spread":false},{"title":"_primary.dbs <span style='color:#111;'> 516B </span>","children":null,"spread":false}],"spread":true},{"title":"@f@s@k2_@t@p","children":[{"title":"_primary.dat <span style='color:#111;'> 719B </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 74B </span>","children":null,"spread":false},{"title":"verilog.rw <span style='color:#111;'> 884B </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 10.04KB </span>","children":null,"spread":false},{"title":"_primary.dbs <span style='color:#111;'> 853B </span>","children":null,"spread":false}],"spread":true},{"title":"@f@s@k2","children":[{"title":"_primary.dat <span style='color:#111;'> 464B </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 232B </span>","children":null,"spread":false},{"title":"_primary.dbs <span style='color:#111;'> 475B </span>","children":null,"spread":false}],"spread":true},{"title":"rom","children":[{"title":"_primary.dat <span style='color:#111;'> 1.04KB </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 206B </span>","children":null,"spread":false},{"title":"verilog.rw <span style='color:#111;'> 256B </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 9.61KB </span>","children":null,"spread":false},{"title":"_primary.dbs <span style='color:#111;'> 1.35KB </span>","children":null,"spread":false}],"spread":true},{"title":"_temp","children":[{"title":"vlogkym3vq <span style='color:#111;'> 504B </span>","children":null,"spread":false},{"title":"vloghwfsia <span style='color:#111;'> 986B </span>","children":null,"spread":false},{"title":"vlogfbrs6x <span style='color:#111;'> 985B </span>","children":null,"spread":false},{"title":"vlog87atb8 <span style='color:#111;'> 1.42KB </span>","children":null,"spread":false}],"spread":true},{"title":"divider","children":[{"title":"_primary.dat <span style='color:#111;'> 387B </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 238B </span>","children":null,"spread":false},{"title":"verilog.rw <span style='color:#111;'> 232B </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 3.51KB </span>","children":null,"spread":false},{"title":"_primary.dbs <span style='color:#111;'> 624B </span>","children":null,"spread":false}],"spread":true},{"title":"@f@s@k1","children":[{"title":"_primary.dat <span style='color:#111;'> 464B </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 232B </span>","children":null,"spread":false},{"title":"_primary.dbs <span style='color:#111;'> 465B </span>","children":null,"spread":false}],"spread":true},{"title":"control","children":[{"title":"_primary.dat <span style='color:#111;'> 298B </span>","children":null,"spread":false},{"title":"_primary.vhd <span style='color:#111;'> 305B </span>","children":null,"spread":false},{"title":"verilog.rw <span style='color:#111;'> 224B </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 3.10KB </span>","children":null,"spread":false},{"title":"_primary.dbs <span style='color:#111;'> 527B </span>","children":null,"spread":false}],"spread":true},{"title":"_info <span style='color:#111;'> 1.72KB </span>","children":null,"spread":false}],"spread":true},{"title":"FSK2.mpf <span style='color:#111;'> 76.79KB </span>","children":null,"spread":false},{"title":"FSK2.cr.mti <span style='color:#111;'> 768B </span>","children":null,"spread":false},{"title":"FSKreport.doc <span style='color:#111;'> 4.05MB </span>","children":null,"spread":false},{"title":"vsim.wlf <span style='color:#111;'> 1000.00KB </span>","children":null,"spread":false},{"title":"FSK2_TP.v.bak <span style='color:#111;'> 578B </span>","children":null,"spread":false},{"title":"AB.PNG <span style='color:#111;'> 54.04KB </span>","children":null,"spread":false},{"title":"FSK2.v <span style='color:#111;'> 1.85KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]