fpga控制cy7c68013a做成的USB2.0

上传者: ctmars | 上传时间: 2021-04-13 10:53:04 | 文件大小: 269KB | 文件类型: RAR
描述用fpga控制cy7c68013a做成的USB2.0接口 工程经过测试没问题。

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[{"title":"( 37 个子文件 269KB ) fpga控制cy7c68013a做成的USB2.0","children":[{"title":"fpga控制cy7c68013a做成的USB2.0","children":[{"title":"simulation","children":[{"title":"modelsim.ini.sav <span style='color:#111;'> 215B </span>","children":null,"spread":false},{"title":"modelsim.ini <span style='color:#111;'> 217B </span>","children":null,"spread":false}],"spread":true},{"title":"designer","children":[{"title":"impl1","children":[{"title":"usb_top.tcl <span style='color:#111;'> 173B </span>","children":null,"spread":false},{"title":"usb_top.pdb <span style='color:#111;'> 46.00KB </span>","children":null,"spread":false},{"title":"usb_top.dtf","children":[{"title":"verify.log <span style='color:#111;'> 233B </span>","children":null,"spread":false}],"spread":true},{"title":"simulation","children":null,"spread":false},{"title":"usb_top.ide_des <span style='color:#111;'> 647B </span>","children":null,"spread":false},{"title":"usb_top_fp","children":[{"title":"usb_top.log <span style='color:#111;'> 964B </span>","children":null,"spread":false},{"title":"projectData","children":[{"title":"usb_top.pdb <span style='color:#111;'> 46.50KB </span>","children":null,"spread":false}],"spread":true},{"title":"$$FlashPro_05028.L$$ <span style='color:#111;'> 1015B </span>","children":null,"spread":false},{"title":"usb_top.pro <span style='color:#111;'> 1.49KB </span>","children":null,"spread":false}],"spread":true},{"title":"usb_top.adb <span style='color:#111;'> 149.50KB </span>","children":null,"spread":false},{"title":"usb_top.pdb.depends <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"designer.log <span style='color:#111;'> 7.88KB </span>","children":null,"spread":false}],"spread":true}],"spread":true},{"title":"hdl","children":[{"title":"usb_write_0103.v <span style='color:#111;'> 2.87KB </span>","children":null,"spread":false},{"title":"usb_read_0103.v <span style='color:#111;'> 2.71KB </span>","children":null,"spread":false},{"title":"usb_top.v <span style='color:#111;'> 3.85KB </span>","children":null,"spread":false}],"spread":true},{"title":"viewdraw","children":[{"title":"sch","children":null,"spread":false},{"title":"sym","children":null,"spread":false},{"title":"vf","children":[{"title":"project.lst <span style='color:#111;'> 48B </span>","children":null,"spread":false}],"spread":true},{"title":"viewdraw.ini <span style='color:#111;'> 1.60KB </span>","children":null,"spread":false},{"title":"wir","children":null,"spread":false}],"spread":true},{"title":"coreconsole","children":null,"spread":false},{"title":"smartgen","children":[{"title":"smartgen.aws <span style='color:#111;'> 366B </span>","children":null,"spread":false}],"spread":true},{"title":"usb_0105.prj <span style='color:#111;'> 4.92KB </span>","children":null,"spread":false},{"title":"constraint","children":null,"spread":false},{"title":"component","children":null,"spread":false},{"title":"phy_synthesis","children":null,"spread":false},{"title":"synthesis","children":[{"title":"stdout.log <span style='color:#111;'> 1.34KB </span>","children":null,"spread":false},{"title":"run_options.txt <span style='color:#111;'> 1.36KB </span>","children":null,"spread":false},{"title":"usb_top.srd <span style='color:#111;'> 24.18KB </span>","children":null,"spread":false},{"title":"usb_top_sdc.sdc <span style='color:#111;'> 376B </span>","children":null,"spread":false},{"title":"usb_top.srr <span style='color:#111;'> 14.78KB </span>","children":null,"spread":false},{"title":"usb_top.edn <span style='color:#111;'> 65.94KB </span>","children":null,"spread":false},{"title":"backup","children":[{"title":"usb_top.srr <span style='color:#111;'> 15.64KB </span>","children":null,"spread":false}],"spread":false},{"title":"coreip","children":null,"spread":false},{"title":"usb_top.srs <span style='color:#111;'> 10.72KB </span>","children":null,"spread":false},{"title":"usb_top.sdf <span style='color:#111;'> 17.59KB </span>","children":null,"spread":false},{"title":"usb_top.map <span style='color:#111;'> 28B </span>","children":null,"spread":false},{"title":"usb_top.areasrr <span style='color:#111;'> 4.55KB </span>","children":null,"spread":false},{"title":"usb_top_syn.prj <span style='color:#111;'> 576B </span>","children":null,"spread":false},{"title":"usb_top.srm <span style='color:#111;'> 196.79KB </span>","children":null,"spread":false},{"title":"usb_top.tlg <span style='color:#111;'> 2.17KB </span>","children":null,"spread":false},{"title":"syntmp","children":[{"title":"usb_top.msg <span style='color:#111;'> 1.62KB </span>","children":null,"spread":false},{"title":"usb_top.plg <span style='color:#111;'> 379B </span>","children":null,"spread":false}],"spread":false}],"spread":false},{"title":"readme.txt <span style='color:#111;'> 305B </span>","children":null,"spread":false},{"title":"stimulus","children":null,"spread":false}],"spread":false}],"spread":true}]

评论信息

  • yaoey1987 :
    如果再加一点开发说明就好了,
    2014-10-30
  • 正宇小狗头 :
    挺不错 ,就是分数要的太高了
    2013-09-30
  • shanjiong :
    程序写的不错,但是我下载进去还是有一些小问题,整个USB2.0工程很完整
    2012-11-19
  • MmikerR :
    非常好的程序,FPGA主程序是用Verilog写得,整个USB2.0工程很完整,就是注解少了,看起来有些费劲,最好能弄个说明文档,说明每个文件夹的具体定义和其中文件的功能。
    2012-10-26

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