AD9959原理图及PCB

[{"title":"（ 70 个子文件 11.5MB ） AD9959原理图及PCB","children":[{"title":"ad9959","children":[{"title":"PCB_Project1.PrjPCBStructure <span style='color:#111;'> 48B </span>","children":null,"spread":false},{"title":"PCB_Project1.PrjPCB <span style='color:#111;'> 38.64KB </span>","children":null,"spread":false},{"title":"Sheet1.SchDoc <span style='color:#111;'> 322.00KB </span>","children":null,"spread":false},{"title":"Project Logs for PCB_Project1","children":[{"title":"PCB2 PCB ECO 2017-8-2 17-12-33.LOG <span style='color:#111;'> 2.55KB </span>","children":null,"spread":false},{"title":"PCB2 PCB ECO 2017-8-2 17-31-10.LOG <span style='color:#111;'> 92B </span>","children":null,"spread":false},{"title":"PCB2 PCB ECO 2017-8-3 15-34-22.LOG <span style='color:#111;'> 1.32KB </span>","children":null,"spread":false},{"title":"PCB2 PCB ECO 2017-8-2 19-50-02.LOG <span style='color:#111;'> 1.24KB </span>","children":null,"spread":false},{"title":"PCB2 PCB ECO 2017-8-2 19-51-56.LOG <span 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</span>","children":null,"spread":false},{"title":"PCB2 PCB ECO 2017-8-2 17-30-03.LOG <span style='color:#111;'> 181B </span>","children":null,"spread":false},{"title":"Sheet1 SCH ECO 2017-8-3 15-26-57.LOG <span style='color:#111;'> 83B </span>","children":null,"spread":false}],"spread":false},{"title":"Sheet2.SchDoc <span style='color:#111;'> 314.00KB </span>","children":null,"spread":false},{"title":"PcbLib1.PcbLib <span style='color:#111;'> 593.50KB </span>","children":null,"spread":false},{"title":"Schlib1.SchLib <span style='color:#111;'> 9.50KB </span>","children":null,"spread":false},{"title":"History","children":[{"title":"PcbLib1.~(15).PcbLib.Zip <span style='color:#111;'> 493.66KB </span>","children":null,"spread":false},{"title":"PcbLib1.~(7).PcbLib.Zip <span style='color:#111;'> 493.81KB </span>","children":null,"spread":false},{"title":"PcbLib1.~(5).PcbLib.Zip <span style='color:#111;'> 493.56KB </span>","children":null,"spread":false},{"title":"PcbLib1.~(6).PcbLib.Zip <span style='color:#111;'> 493.72KB </span>","children":null,"spread":false},{"title":"PCB2.~(4).PcbDoc.Zip <span style='color:#111;'> 758.72KB </span>","children":null,"spread":false},{"title":"PCB2.~(6).PcbDoc.Zip <span style='color:#111;'> 853.11KB </span>","children":null,"spread":false},{"title":"Sheet2.~(7).SchDoc.Zip <span style='color:#111;'> 33.63KB </span>","children":null,"spread":false},{"title":"Schlib1.~(3).SchLib.Zip <span style='color:#111;'> 2.13KB </span>","children":null,"spread":false},{"title":"PcbLib1.~(12).PcbLib.Zip <span style='color:#111;'> 493.75KB </span>","children":null,"spread":false},{"title":"Schlib1.~(2).SchLib.Zip <span style='color:#111;'> 1.95KB </span>","children":null,"spread":false},{"title":"PcbLib1.~(2).PcbLib.Zip <span style='color:#111;'> 9.90KB </span>","children":null,"spread":false},{"title":"PcbLib1.~(17).PcbLib.Zip <span style='color:#111;'> 12.34KB </span>","children":null,"spread":false},{"title":"Sheet2.~(5).SchDoc.Zip <span style='color:#111;'> 33.46KB </span>","children":null,"spread":false},{"title":"PCB2.~(3).PcbDoc.Zip <span style='color:#111;'> 841.52KB </span>","children":null,"spread":false},{"title":"Sheet2.~(6).SchDoc.Zip <span style='color:#111;'> 33.35KB </span>","children":null,"spread":false},{"title":"Sheet1.~(1).SchDoc.Zip <span style='color:#111;'> 27.31KB </span>","children":null,"spread":false},{"title":"PcbLib1.~(16).PcbLib.Zip <span style='color:#111;'> 11.05KB </span>","children":null,"spread":false},{"title":"PCB2.~(2).PcbDoc.Zip <span style='color:#111;'> 748.76KB </span>","children":null,"spread":false},{"title":"Sheet1.~(2).SchDoc.Zip <span style='color:#111;'> 27.36KB </span>","children":null,"spread":false},{"title":"PcbLib1.~(10).PcbLib.Zip <span style='color:#111;'> 493.80KB </span>","children":null,"spread":false},{"title":"PCB2.~(5).PcbDoc.Zip <span style='color:#111;'> 759.03KB </span>","children":null,"spread":false},{"title":"Schlib1.~(1).SchLib.Zip <span style='color:#111;'> 1.80KB </span>","children":null,"spread":false},{"title":"PCB2.~(1).PcbDoc.Zip <span style='color:#111;'> 14.57KB </span>","children":null,"spread":false},{"title":"PcbLib1.~(14).PcbLib.Zip <span style='color:#111;'> 493.71KB </span>","children":null,"spread":false},{"title":"PcbLib1.~(4).PcbLib.Zip <span style='color:#111;'> 493.59KB </span>","children":null,"spread":false},{"title":"Sheet2.~(1).SchDoc.Zip <span style='color:#111;'> 1.42KB </span>","children":null,"spread":false},{"title":"PcbLib1.~(8).PcbLib.Zip <span style='color:#111;'> 493.77KB </span>","children":null,"spread":false},{"title":"Sheet2.~(2).SchDoc.Zip <span style='color:#111;'> 30.65KB </span>","children":null,"spread":false},{"title":"Sheet2.~(8).SchDoc.Zip <span style='color:#111;'> 33.63KB </span>","children":null,"spread":false},{"title":"Sheet2.~(3).SchDoc.Zip <span style='color:#111;'> 30.85KB </span>","children":null,"spread":false},{"title":"Sheet2.~(4).SchDoc.Zip <span style='color:#111;'> 30.84KB </span>","children":null,"spread":false},{"title":"PcbLib1.~(3).PcbLib.Zip <span style='color:#111;'> 9.86KB </span>","children":null,"spread":false},{"title":"PcbLib1.~(9).PcbLib.Zip <span style='color:#111;'> 493.81KB </span>","children":null,"spread":false},{"title":"PcbLib1.~(13).PcbLib.Zip <span style='color:#111;'> 493.71KB </span>","children":null,"spread":false},{"title":"PcbLib1.~(11).PcbLib.Zip <span style='color:#111;'> 493.74KB </span>","children":null,"spread":false},{"title":"PCB_Project1.~(1).PrjPCB.Zip <span style='color:#111;'> 4.23KB </span>","children":null,"spread":false},{"title":"PcbLib1.~(1).PcbLib.Zip <span style='color:#111;'> 8.35KB </span>","children":null,"spread":false}],"spread":false},{"title":"__Previews","children":[{"title":"Sheet1.SchDocPreview <span style='color:#111;'> 45.41KB </span>","children":null,"spread":false},{"title":"Sheet2.SchDocPreview <span style='color:#111;'> 96.48KB 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