基于verilogHDL的AES加密解密程序

[{"title":"（ 17 个子文件 469KB ） 基于verilogHDL的AES加密解密程序","children":[{"title":"AES-based-on-FPGA-master","children":[{"title":"LICENSE <span style='color:#111;'> 1.04KB </span>","children":null,"spread":false},{"title":"AES_verilog_demo","children":[{"title":"ROM_2P","children":[{"title":"AES_sTable.mif <span style='color:#111;'> 4.64KB </span>","children":null,"spread":false}],"spread":true},{"title":"RTL","children":[{"title":"roundFunc_10.v <span style='color:#111;'> 429B </span>","children":null,"spread":false},{"title":"colMix_keyAdd.v <span style='color:#111;'> 766B </span>","children":null,"spread":false},{"title":"code_connect.png <span style='color:#111;'> 31.15KB </span>","children":null,"spread":false},{"title":"subByte_rowShift.v <span style='color:#111;'> 2.10KB </span>","children":null,"spread":false},{"title":"subColMix.v <span style='color:#111;'> 899B </span>","children":null,"spread":false},{"title":"AES_encryp_top.v <span style='color:#111;'> 4.46KB </span>","children":null,"spread":false},{"title":"代码关系图.png <span style='color:#111;'> 31.15KB </span>","children":null,"spread":false},{"title":"roundFunc.v <span style='color:#111;'> 447B </span>","children":null,"spread":false},{"title":"keyExp.v <span style='color:#111;'> 1.66KB </span>","children":null,"spread":false}],"spread":true},{"title":"simulation","children":[{"title":"AES_encryp_top.vt <span style='color:#111;'> 2.49KB </span>","children":null,"spread":false},{"title":"仿真图1.png <span style='color:#111;'> 145.70KB </span>","children":null,"spread":false},{"title":"仿真图3.png <span style='color:#111;'> 133.51KB </span>","children":null,"spread":false},{"title":"仿真图2.png <span style='color:#111;'> 150.37KB </span>","children":null,"spread":false},{"title":"AES调试数据_1.txt <span style='color:#111;'> 3.81KB </span>","children":null,"spread":false}],"spread":true},{"title":"README.md <span style='color:#111;'> 1.11KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}],"spread":true}]