[{"title":"( 36 个子文件 70KB ) 以太网控制器Verilog源码(含有MAC,MII接口)","children":[{"title":"以太网控制器Verilog源码(含有MAC,MII接口)","children":[{"title":"rtl","children":[{"title":"verilog","children":[{"title":"Phy_int.v <span style='color:#111;'> 8.38KB </span>","children":null,"spread":false},{"title":"MAC_tx.v <span style='color:#111;'> 12.85KB </span>","children":null,"spread":false},{"title":"RMON","children":[{"title":"RMON_addr_gen.v <span style='color:#111;'> 11.15KB </span>","children":null,"spread":false},{"title":"RMON_ctrl.v <span style='color:#111;'> 9.92KB </span>","children":null,"spread":false},{"title":"RMON_dpram.v <span style='color:#111;'> 1.26KB </span>","children":null,"spread":false}],"spread":true},{"title":"MAC_top.v <span style='color:#111;'> 20.15KB </span>","children":null,"spread":false},{"title":"reg_int.v <span style='color:#111;'> 10.04KB </span>","children":null,"spread":false},{"title":"eth_miim.v <span style='color:#111;'> 16.25KB </span>","children":null,"spread":false},{"title":"MAC_rx.v <span style='color:#111;'> 11.89KB </span>","children":null,"spread":false},{"title":"RMON.v <span style='color:#111;'> 9.06KB </span>","children":null,"spread":false},{"title":"MAC_rx","children":[{"title":"MAC_rx_add_chk.v <span style='color:#111;'> 6.66KB </span>","children":null,"spread":false},{"title":"Broadcast_filter.v <span style='color:#111;'> 5.10KB </span>","children":null,"spread":false},{"title":"MAC_rx_ctrl.v <span style='color:#111;'> 21.84KB </span>","children":null,"spread":false},{"title":"CRC_chk.v <span style='color:#111;'> 6.13KB </span>","children":null,"spread":false},{"title":"MAC_rx_FF.v <span style='color:#111;'> 24.26KB </span>","children":null,"spread":false}],"spread":true},{"title":"Clk_ctrl.v <span style='color:#111;'> 5.19KB </span>","children":null,"spread":false},{"title":"MAC_tx","children":[{"title":"Ramdon_gen.v <span style='color:#111;'> 5.48KB </span>","children":null,"spread":false},{"title":"MAC_tx_Ctrl.v <span style='color:#111;'> 22.50KB </span>","children":null,"spread":false},{"title":"flow_ctrl.v <span style='color:#111;'> 7.65KB </span>","children":null,"spread":false},{"title":"CRC_gen.v <span style='color:#111;'> 7.17KB </span>","children":null,"spread":false},{"title":"MAC_tx_FF.v <span style='color:#111;'> 25.88KB </span>","children":null,"spread":false},{"title":"MAC_tx_addr_add.v <span style='color:#111;'> 5.80KB </span>","children":null,"spread":false}],"spread":true},{"title":"miim","children":[{"title":"eth_shiftreg.v <span style='color:#111;'> 6.75KB </span>","children":null,"spread":false},{"title":"timescale.v <span style='color:#111;'> 3.15KB </span>","children":null,"spread":false},{"title":"eth_outputcontrol.v <span style='color:#111;'> 6.34KB </span>","children":null,"spread":false},{"title":"eth_clockgen.v <span style='color:#111;'> 5.54KB </span>","children":null,"spread":false}],"spread":false},{"title":"TECH","children":[{"title":"CLK_DIV2.v <span style='color:#111;'> 3.51KB </span>","children":null,"spread":false},{"title":"CLK_SWITCH.v <span style='color:#111;'> 3.45KB </span>","children":null,"spread":false},{"title":"xilinx","children":[{"title":"CLK_DIV2.v <span style='color:#111;'> 3.57KB </span>","children":null,"spread":false},{"title":"CLK_SWITCH.v <span style='color:#111;'> 3.63KB </span>","children":null,"spread":false},{"title":"duram.v <span style='color:#111;'> 1.49KB </span>","children":null,"spread":false}],"spread":false},{"title":"altera","children":[{"title":"CLK_DIV2.v <span style='color:#111;'> 3.57KB </span>","children":null,"spread":false},{"title":"CLK_SWITCH.v <span style='color:#111;'> 3.50KB </span>","children":null,"spread":false},{"title":"duram.v <span style='color:#111;'> 2.35KB </span>","children":null,"spread":false}],"spread":false},{"title":"duram.v <span style='color:#111;'> 2.35KB </span>","children":null,"spread":false}],"spread":false},{"title":"header.v <span style='color:#111;'> 190B </span>","children":null,"spread":false}],"spread":false}],"spread":true}],"spread":true}],"spread":true}]