TI ds90cr288a器件手册

The DS90CR287 transmitter converts 28 bits of • 20 to 85 MHz Shift Clock Support LVCMOS/LVTTL data into four LVDS (Low Voltage • 50% Duty Cycle on Receiver Output Clock Differential Signaling) data streams. A phase-locked • 2.5 / 0 ns Set & Hold Times on TxINPUTs transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the • Low Power Consumption transmit clock 28 bits of input data are sampled and • ±1V Common-Mode Range (around +1.2V) transmitted. • Narrow Bus Reduces Cable Size and Cost The DS90CR288A receiver converts the four LVDS • Up to 2.38 Gbps Throughput data streams back into 28 bits of LVCMOS/LVTTL • Up to 297.5 Mbytes/sec Bandwidth data. At a transmit clock frequency of 85 MHz, 28 bits of TTL data are transmitted at a rate of 595 Mbps per • 345 mV (typ) Swing LVDS Devices for Low EMI LVDS data channel. Using a 85 MHz clock, the data • PLL Requires no External Components throughput is 2.38 Gbit/s (297.5 Mbytes/sec). • Rising Edge Data Strobe This chipset is an ideal means to solve EMI and • Compatible with TIA/EIA-644 LVDS Standard cable size problems associated with wide, high-speed • Low Profile 56-Lead TSSOP Package TTL interfaces.