SDRAM的IP核VerilogHDL源代码

[{"title":"（ 8 个子文件 27KB ） SDRAM的IP核VerilogHDL源代码","children":[{"title":"SDRAM","children":[{"title":"micro.v <span style='color:#111;'> 11.52KB </span>","children":null,"spread":false},{"title":"tst_inc.h <span style='color:#111;'> 5.10KB </span>","children":null,"spread":false},{"title":"sdram.v <span style='color:#111;'> 17.83KB </span>","children":null,"spread":false},{"title":"inc.h <span style='color:#111;'> 9.54KB </span>","children":null,"spread":false},{"title":"hostcont.v <span style='color:#111;'> 17.87KB </span>","children":null,"spread":false},{"title":"readme <span style='color:#111;'> 9.54KB </span>","children":null,"spread":false},{"title":"tst_ inc.v <span style='color:#111;'> 5.10KB </span>","children":null,"spread":false},{"title":"sdramcnt.v <span style='color:#111;'> 22.87KB </span>","children":null,"spread":false}],"spread":true}],"spread":true}]