aes加密算法源码

[{"title":"（ 78 个子文件 787KB ） aes加密算法源码","children":[{"title":"aes c++ and verilog 文件包","children":[{"title":"AES C++代码","children":[{"title":"ReadMe.txt <span style='color:#111;'> 1.18KB </span>","children":null,"spread":false},{"title":"StdAfx.h <span style='color:#111;'> 667B </span>","children":null,"spread":false},{"title":"cipher.plg <span style='color:#111;'> 1.19KB </span>","children":null,"spread":false},{"title":"Ecryption.opt <span style='color:#111;'> 47.50KB </span>","children":null,"spread":false},{"title":"cipher.sdf <span style='color:#111;'> 1.64MB </span>","children":null,"spread":false},{"title":"chart.cpp <span style='color:#111;'> 3.01KB </span>","children":null,"spread":false},{"title":"Ecryption.h <span style='color:#111;'> 720B </span>","children":null,"spread":false},{"title":"Ecryption.plg <span style='color:#111;'> 930B </span>","children":null,"spread":false},{"title":"cipher.vcxproj.filters <span style='color:#111;'> 1.53KB </span>","children":null,"spread":false},{"title":"Debug","children":[{"title":"chart.obj <span style='color:#111;'> 6.45KB </span>","children":null,"spread":false},{"title":"vc60.pdb <span style='color:#111;'> 68.00KB </span>","children":null,"spread":false},{"title":"Ecryption.sbr <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"decryption.sbr <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"cipher.ilk <span style='color:#111;'> 209.40KB </span>","children":null,"spread":false},{"title":"Ecryption.pdb <span style='color:#111;'> 25.00KB </span>","children":null,"spread":false},{"title":"Ecryption.pch <span style='color:#111;'> 215.47KB </span>","children":null,"spread":false},{"title":"cipher.obj <span style='color:#111;'> 3.38KB </span>","children":null,"spread":false},{"title":"vc60.idb <span style='color:#111;'> 73.00KB </span>","children":null,"spread":false},{"title":"StdAfx.sbr <span style='color:#111;'> 359B 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</span>","children":null,"spread":false},{"title":"cipher.dsp <span style='color:#111;'> 4.68KB </span>","children":null,"spread":false},{"title":"Ecryption.dsp <span style='color:#111;'> 3.36KB </span>","children":null,"spread":false},{"title":"Ecryption.cpp <span style='color:#111;'> 3.23KB </span>","children":null,"spread":false},{"title":"cipher.sln <span style='color:#111;'> 878B </span>","children":null,"spread":false},{"title":"cipher.ncb <span style='color:#111;'> 89.00KB </span>","children":null,"spread":false},{"title":"cipher.dsw <span style='color:#111;'> 537B </span>","children":null,"spread":false},{"title":"Ecryption.dsw <span style='color:#111;'> 526B </span>","children":null,"spread":false},{"title":"cipher.opt <span style='color:#111;'> 49.50KB </span>","children":null,"spread":false},{"title":"cipher.cpp <span style='color:#111;'> 293B </span>","children":null,"spread":false},{"title":"cipher.vcxproj.user <span style='color:#111;'> 143B </span>","children":null,"spread":false},{"title":"StdAfx.cpp <span style='color:#111;'> 293B </span>","children":null,"spread":false},{"title":"cipher.vcproj <span style='color:#111;'> 6.95KB </span>","children":null,"spread":false},{"title":"cipher.vcxproj <span style='color:#111;'> 7.05KB </span>","children":null,"spread":false},{"title":"in.txt <span style='color:#111;'> 33B </span>","children":null,"spread":false},{"title":"cipher.suo <span style='color:#111;'> 9.50KB </span>","children":null,"spread":false},{"title":"cipher.vcproj.WIN-20130501WUK.Administrator.user <span style='color:#111;'> 1.39KB </span>","children":null,"spread":false},{"title":"decryption.cpp <span style='color:#111;'> 1.48KB </span>","children":null,"spread":false}],"spread":false},{"title":"AES Verilog HDL代码","children":[{"title":"AES","children":[{"title":"AES.mpf <span style='color:#111;'> 27.53KB </span>","children":null,"spread":false},{"title":"tab.v <span style='color:#111;'> 4.08KB </span>","children":null,"spread":false},{"title":"AES.cr.mti <span style='color:#111;'> 1.77KB </span>","children":null,"spread":false},{"title":"KeyExpansion.v <span style='color:#111;'> 1.29KB </span>","children":null,"spread":false},{"title":"aesmain.v <span style='color:#111;'> 782B </span>","children":null,"spread":false},{"title":"SubBytes.v <span style='color:#111;'> 1.39KB </span>","children":null,"spread":false},{"title":"sh.v <span style='color:#111;'> 4.32KB </span>","children":null,"spread":false},{"title":"vsim.wlf <span style='color:#111;'> 40.00KB </span>","children":null,"spread":false},{"title":"work","children":[{"title":"keyexpansion","children":[{"title":"_primary.vhd <span style='color:#111;'> 349B </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 19.53KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 1.65KB </span>","children":null,"spread":false}],"spread":true},{"title":"mixclomn","children":[{"title":"_primary.vhd <span style='color:#111;'> 212B </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 27.95KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 3.43KB </span>","children":null,"spread":false}],"spread":true},{"title":"_info <span style='color:#111;'> 1.72KB </span>","children":null,"spread":false},{"title":"sh","children":[{"title":"_primary.vhd <span style='color:#111;'> 196B </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 22.01KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 9.61KB </span>","children":null,"spread":false}],"spread":false},{"title":"testaes","children":[{"title":"_primary.vhd <span style='color:#111;'> 74B </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 5.59KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 548B </span>","children":null,"spread":false}],"spread":false},{"title":"aesmain","children":[{"title":"_primary.vhd <span style='color:#111;'> 399B </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 9.30KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 803B </span>","children":null,"spread":false}],"spread":false},{"title":"subsbyte","children":[{"title":"_primary.vhd <span style='color:#111;'> 212B </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 13.65KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 1.99KB </span>","children":null,"spread":false}],"spread":false},{"title":"tab","children":[{"title":"_primary.vhd <span style='color:#111;'> 198B </span>","children":null,"spread":false},{"title":"verilog.asm <span style='color:#111;'> 21.80KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 9.52KB </span>","children":null,"spread":false}],"spread":false}],"spread":true},{"title":"MixColumns.v <span style='color:#111;'> 2.52KB </span>","children":null,"spread":false},{"title":"testaes.v <span style='color:#111;'> 576B </span>","children":null,"spread":false}],"spread":false}],"spread":true}],"spread":true}],"spread":true}]