Cyclone10 FPGA读写eeprom(Quartus17.1工程Quartus17.1工程文件+文档资料

Cyclone10 FPGA读写eeprom(24lc04)实验Verilog源码Quartus17.1工程文件+文档资料, FPGA为CYCLONE10LP系列中的10CL025YU256C8. 完整的Quartus工程文件，可以做为你的学习设计参考。 module i2c_master_top ( input rst, input clk, input[15:0] clk_div_cnt, // I2C signals // i2c clock line input scl_pad_i, // SCL-line input output scl_pad_o, // SCL-line output(always 1'b0) output scl_padoen_o, // SCL-line output enable(active low) // i2c data line input sda_pad_i, // SDA-line input output sda_pad_o, // SDA-line output (always 1'b0) output sda_padoen_o, // SDA-line output enable (active low) input i2c_addr_2byte, input i2c_read_req, output i2c_read_req_ack, input i2c_write_req, output i2c_write_req_ack, input[7:0] i2c_slave_dev_addr, //device address input[15:0]i2c_slave_reg_addr, //word address input[7:0] i2c_write_data, output reg[7:0]i2c_read_data, output reg error ); localparam S_IDLE = 0; localparam S_WR_DEV_ADDR = 1; localparam S_WR_REG_ADDR = 2; localparam S_WR_DATA = 3; localparam S_WR_ACK = 4; localparam S_WR_ERR_NACK = 5; localparam S_RD_DEV_ADDR0 = 6; localparam S_RD_REG_ADDR = 7; localparam S_RD_DEV_ADDR1 = 8; localparam S_RD_DATA = 9; localparam S_RD_STOP = 10; localparam S_WR_STOP = 11; localparam S_WAIT = 12; localparam S_WR_REG_ADDR1 = 13; localparam S_RD_REG_ADDR1 = 14; localparam S_RD_ACK = 15; reg start; reg stop; reg read; reg write; reg ack_in; reg[7:0] txr; wire[7:0] rxr; wire i2c_busy; //It was high level after start signal and low level after stop signal wire i2c_al; //arbitrament lose(The stop signal is detected but no signal is requested.The host setting SDA is high,Actual SDA is low) wire done; wire irxack; //slave receive the respond，0 (receive)，1(refuse) reg[3:0] state,next_state; assign i2c_read