SD卡读写Cyclone10 FPGA实验Verilog源码Quartus17.1工程文件+文档资料.zip

SD卡读写Cyclone10 FPGA实验Verilog源码Quartus17.1工程文件+文档资料, FPGA为CYCLONE10LP系列中的10CL025YU256C8. 完整的Quartus工程文件，可以做为你的学习设计参考。 module sd_card_test( input clk, input rst_n, input key, output sd_ncs, output sd_dclk, output sd_mosi, input sd_miso, output [3:0] led ); parameter S_IDLE = 0; parameter S_READ = 1; parameter S_WRITE = 2; parameter S_END = 3; reg[3:0] state; wire sd_init_done; reg sd_sec_read; wire[31:0] sd_sec_read_addr; wire[7:0] sd_sec_read_data; wire sd_sec_read_data_valid; wire sd_sec_read_end; reg sd_sec_write; wire[31:0] sd_sec_write_addr; reg [7:0] sd_sec_write_data; wire sd_sec_write_data_req; wire sd_sec_write_end; reg[9:0] wr_cnt; reg[9:0] rd_cnt; wire button_negedge; reg[7:0] read_data; assign sd_sec_read_addr = 32'd0; assign sd_sec_write_addr = 32'd0; assign led = ~read_data[3:0]; ax_debounce ax_debounce_m0 ( .clk (clk), .rst (~rst_n), .button_in (key), .button_posedge (), .button_negedge (button_negedge), .button_out () ); always@(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) wr_cnt <= 10'd0; else if(state == S_WRITE) begin if(sd_sec_write_data_req == 1'b1) wr_cnt <= wr_cnt + 10'd1; end else wr_cnt <= 10'd0; end always@(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) rd_cnt <= 10'd0; else if(state == S_READ) begin if(sd_sec_read_data_valid == 1'b1) rd_cnt <= rd_cnt + 10'd1; end else rd_cnt <= 10'd0; end always@(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) read_data <= 8'd0; else if(state == S_READ) begin if(sd_sec_read_data_valid == 1'b1 && rd_cnt == 10'd0) read_data <= sd_se