[{"title":"( 4 个子文件 1.1MB ) FPGA Verilog 实现160MHz高速SPI通信:主机与从机源码解析","children":[{"title":"FPGA Verilog 实现160MHz高速SPI通信:主机与从机源码解析.pdf <span style='color:#111;'> 109.02KB </span>","children":null,"spread":false},{"title":"FPGA","children":[{"title":"2.jpg <span style='color:#111;'> 263.71KB </span>","children":null,"spread":false},{"title":"1.jpg <span style='color:#111;'> 156.07KB </span>","children":null,"spread":false}],"spread":true},{"title":"FPGA Verilog SPI主机源码(实测160M无时序问题,含送从机代码).docx <span style='color:#111;'> 37.42KB </span>","children":null,"spread":false}],"spread":true}]