Python自动生成Verilog例化模板的工具.zip

[{"title":"（ 29 个子文件 1.33MB ） Python自动生成Verilog例化模板的工具.zip","children":[{"title":"Python自动生成Verilog例化模板的工具","children":[{"title":"Method2","children":[{"title":"inst_test_gen.v <span style='color:#111;'> 845B </span>","children":null,"spread":false},{"title":"module_gen_def.pyc <span style='color:#111;'> 2.76KB </span>","children":null,"spread":false},{"title":"tx_pack.v <span style='color:#111;'> 2.56KB </span>","children":null,"spread":false},{"title":"test_gen.py <span style='color:#111;'> 582B </span>","children":null,"spread":false},{"title":"module_gen_def.py <span style='color:#111;'> 3.29KB </span>","children":null,"spread":false}],"spread":true},{"title":"ReadMe.txt <span style='color:#111;'> 770B </span>","children":null,"spread":false},{"title":"README.md <span style='color:#111;'> 3.12KB </span>","children":null,"spread":false},{"title":"Method1_recommend","children":[{"title":"genHdlInst.run.py <span style='color:#111;'> 5.04KB </span>","children":null,"spread":false},{"title":"inst_frame_gen_k7.v <span style='color:#111;'> 610B </span>","children":null,"spread":false},{"title":"frame_gen_k7.v <span style='color:#111;'> 1.82KB </span>","children":null,"spread":false},{"title":"genHdlInst.py <span style='color:#111;'> 5.14KB </span>","children":null,"spread":false}],"spread":true},{"title":"Method3","children":[{"title":"mainwindow.ui <span style='color:#111;'> 3.83KB </span>","children":null,"spread":false},{"title":"inst_top.v <span style='color:#111;'> 1.13KB </span>","children":null,"spread":false},{"title":"gif","children":[{"title":"FpgaTool.gif <span style='color:#111;'> 975.22KB </span>","children":null,"spread":false},{"title":"genHdlInst.gif <span style='color:#111;'> 369.84KB </span>","children":null,"spread":false}],"spread":true},{"title":"top.v <span style='color:#111;'> 2.15KB </span>","children":null,"spread":false},{"title":"syntax_highlight.py <span style='color:#111;'> 6.21KB </span>","children":null,"spread":false},{"title":"pic","children":[{"title":"openfile.png <span style='color:#111;'> 222B </span>","children":null,"spread":false},{"title":"newfile.png <span style='color:#111;'> 1.44KB </span>","children":null,"spread":false},{"title":"gen_inst.png <span style='color:#111;'> 734B </span>","children":null,"spread":false},{"title":"savefile.png <span style='color:#111;'> 2.03KB </span>","children":null,"spread":false},{"title":"fpga.png <span style='color:#111;'> 1.45KB </span>","children":null,"spread":false},{"title":"text.png <span style='color:#111;'> 198B </span>","children":null,"spread":false},{"title":"gen_format.png <span style='color:#111;'> 1.34KB </span>","children":null,"spread":false}],"spread":true},{"title":"README.md <span style='color:#111;'> 633B </span>","children":null,"spread":false},{"title":"genHdlInst.py <span style='color:#111;'> 5.14KB </span>","children":null,"spread":false},{"title":"FpgaTool.py <span style='color:#111;'> 3.89KB </span>","children":null,"spread":false},{"title":".gitignore <span style='color:#111;'> 34B </span>","children":null,"spread":false},{"title":"mainwindow.py <span style='color:#111;'> 5.71KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}],"spread":true}]