VGA显示一个小方块移动 FPGA(EP4CE6)实验Verilog逻辑源码Quartus工程文件+文档资料.rar
VGA显示一个小方块,FPGA(EP4CE6)实验Verilog逻辑源码Quartus工程文件+文档资料,FPGA为CYCLONE4系列中的EP4CE6E22C8. 完整的工程文件，可以做为你的学习设计参考。
********************************************************************************************************/
//上电后，VGA显示一个移动的小块，碰到边框的时候被弹开。
module VGA_Moving_Block (
input sys_clk ,
input sys_rst_n ,
output wire Hs ,
output wire Vs ,
output wire VGA_G ,
output wire VGA_B ,
output wire VGA_R );
//Reg define
reg sys_clk_pixel ;
reg [9:0] x_count ;
reg [9:0] y_count ;
reg hsync ;
reg vsync ;
reg [17:0] clk_cnt ;
reg clkout ;
reg up_down_x;
reg up_down_y; //上升和下降信号
reg [9:0] x_pos ; //小方块左上角坐标
reg [9:0] y_pos ; //小方块左上角坐标
//Wire define
wire valid_mov;
wire valid_1 ;
wire valid_2 ;
wire valid_3 ;
wire valid_4 ;
wire valid_s ;
//************************************************************************************
//** Main Program
//**
//************************************************************************************
//像素时钟 分频产生 25Mhz 时钟
always @ (posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n)
sys_clk_pixel <= 1'b0;
else
sys_clk_pixel <= ~sys_clk_pixel;
end
//行坐标和纵坐标
always @ (posedge sys_clk_pixel) begin
if (!sys_rst_n) begin
x_count <= 0;
y_count <= 0;
end
else if (x_count == 10'd799) begin
x_count <= 10'd0;
if (y_count == 10'd519)
y_count <= 10'd0;
else
y_count <= y_count+1'b1;
end
else
x_count <= x_count+1'b1;
end
//同步信号
always @ (posedge sys_clk_pixel) begin
if (x_count <= 10'd95)
hsync <= 1'b0;
else
hsync <= 1'b1;
end
always @ (posedge sys_clk_pixel) begin
if (y_count <= 1'd1)
vsync <= 1'b0;
else
vsync <= 1'b1;
end
assign Hs = hsync;
assign
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