同步4位可逆计数器Cyclone4E FPGA设计Verilog逻辑源码Quartus工程文件.zip
同步4位可逆计数器Cyclone4E FPGA设计Verilog逻辑源码Quartus工程文件， Quartus软件版本11.0, FPGA型号为CYCLONE4E系列中的EP4CE6E22C8,可以做为你的学习设计参考。
module cnt_kn(clk,clr,s,en,updn,d,co,q);
input clk,clr,s,en,updn; //输入时钟、清零端(高电平有效)、置数端（高电平有效）、使能端、计数器方向控制端
input[3:0] d; //预置数据端
output[3:0] q; //计数输出端
output co; //进位端
reg[3:0] q; //计数输出寄存器
reg co; //进位输出寄存器
always@(posedge clk) //时钟上升沿触发
begin
if(clr) //判断清零端是否有效
begin
q<=0; //q置0
end
else
begin
if(s) //判断置数端是否有效
begin
q<=d; //q置d中的数据
end
else
if(en) //判断使能端是否有效
begin
if(updn) //判断方向寄存器是否为1
begin
if(q==4'b1111) //判断q是否为15
begin
q<=4'b0000; //q清0
co<=1; //co置1
end
else //q还没到15
begin
q<=q+1; //q自加1
co<=0; //co置0
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本站所有资源不代表本站的观点或立场，基于网友分享，根据中国法律《信息网络传播权保护条例》第二十二条之规定，若资源存在侵权或相关问题请联系本站客服人员，zhiweidada#qq.com，请把#换成@，本站将给予最大的支持与配合，做到及时反馈和处理。关于更多版权及免责申明参见 版权及免责申明