[{"title":"( 1081 个子文件 7.64MB ) EPM240 CPLD开发板Verilog HDL设计实验例程15例Quartus 13.1工程+设计说明文档.zip","children":[{"title":"MAX II的UFM模块使用实例.pdf <span style='color:#111;'> 286.83KB </span>","children":null,"spread":false},{"title":"ufmtest.fit.smsg <span style='color:#111;'> 370B </span>","children":null,"spread":false},{"title":"ufmtest.pof <span style='color:#111;'> 14.68KB </span>","children":null,"spread":false},{"title":"ufmtest.v <span style='color:#111;'> 812B </span>","children":null,"spread":false},{"title":"ufmtest_assignment_defaults.qdf <span style='color:#111;'> 46.39KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多,未全部展示</span>","children":null,"spread":false}],"spread":true}]