Altera_stratixVGX_5sgxea7kf40_fpga开发板资料Cadence硬件原理图+PCB+Verilog例程源码+文档资料.zip

[{"title":"（ 478 个子文件 297MB ） Altera_stratixVGX_5sgxea7kf40_fpga开发板资料Cadence硬件原理图+PCB+Verilog例程源码+文档资料.zip","children":[{"title":"restore.sh <span style='color:#111;'> 1.98KB </span>","children":null,"spread":false},{"title":"restore_s5gxea7_fpga_bup.flash <span style='color:#111;'> 81.19MB </span>","children":null,"spread":false},{"title":"max5.pof <span style='color:#111;'> 43.68KB </span>","children":null,"spread":false},{"title":"boot_code.srec <span style='color:#111;'> 220B </span>","children":null,"spread":false},{"title":"boot_code.s <span style='color:#111;'> 6.05KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]