Verilog HDl语言实现CPLD-EPC240与电脑的串口通讯QUARTUS逻辑工程源码.zip

[{"title":"（ 70 个子文件 436KB ） Verilog HDl语言实现CPLD-EPC240与电脑的串口通讯QUARTUS逻辑工程源码.zip","children":[{"title":"用Verilog HDl语言实现CPLD与电脑的串口通讯","children":[{"title":"serial","children":[{"title":"serial.cdf <span style='color:#111;'> 390B </span>","children":null,"spread":false},{"title":"serial.pin <span style='color:#111;'> 15.02KB </span>","children":null,"spread":false},{"title":"serial.qws <span style='color:#111;'> 1.04KB </span>","children":null,"spread":false},{"title":"serial.fit.rpt <span style='color:#111;'> 66.92KB </span>","children":null,"spread":false},{"title":"db","children":[{"title":"serial.lpc.html <span style='color:#111;'> 430B </span>","children":null,"spread":false},{"title":"serial.db_info <span style='color:#111;'> 151B </span>","children":null,"spread":false},{"title":"serial.pre_map.hdb <span style='color:#111;'> 11.40KB </span>","children":null,"spread":false},{"title":"add_sub_5ph.tdf <span style='color:#111;'> 5.91KB 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