用Verilog（FPGA）实现USB源码+上位机+驱动.zip

[{"title":"（ 81 个子文件 159KB ） 用Verilog（FPGA）实现USB源码+上位机+驱动.zip","children":[{"title":"用Verilog（FPGA）实现USB源码+上位机+驱动","children":[{"title":"使用说明.txt <span style='color:#111;'> 49B </span>","children":null,"spread":false},{"title":"USB","children":[{"title":"Application","children":[{"title":"cube.clw <span style='color:#111;'> 2.51KB </span>","children":null,"spread":false},{"title":"resource.h <span style='color:#111;'> 778B </span>","children":null,"spread":false},{"title":"InputDialog.h <span style='color:#111;'> 1.21KB </span>","children":null,"spread":false},{"title":"cube.dsw <span style='color:#111;'> 531B </span>","children":null,"spread":false},{"title":"Cube.aps <span style='color:#111;'> 23.82KB </span>","children":null,"spread":false},{"title":"cube.cpp <span style='color:#111;'> 3.60KB </span>","children":null,"spread":false},{"title":"cube.opt <span style='color:#111;'> 49.50KB </span>","children":null,"spread":false},{"title":"stdafx.h <span style='color:#111;'> 623B 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9.67KB </span>","children":null,"spread":false},{"title":"RequestHandler.vhd <span style='color:#111;'> 3.37KB </span>","children":null,"spread":false},{"title":"IOSwitch.jhd <span style='color:#111;'> 17B </span>","children":null,"spread":false},{"title":"automake.log <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"EdgeController.jhd <span style='color:#111;'> 23B </span>","children":null,"spread":false},{"title":"USBSoftLock.jhd <span style='color:#111;'> 163B </span>","children":null,"spread":false},{"title":"usbsoftlock_TB.jhd <span style='color:#111;'> 49B </span>","children":null,"spread":false},{"title":"DeviceTranseiver.vhd <span style='color:#111;'> 21.63KB </span>","children":null,"spread":false},{"title":"Firmware.ptf <span style='color:#111;'> 33B </span>","children":null,"spread":false},{"title":"DeviceTranseiver.jhd <span style='color:#111;'> 25B </span>","children":null,"spread":false},{"title":"USBSoftLock_ucf.ucf <span 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