【EDA】FIFO缓存器Verilog及testbench

[{"title":"（ 122 个子文件 7.73MB ） 【EDA】FIFO缓存器Verilog及testbench","children":[{"title":"FIFO.qsf <span style='color:#111;'> 3.77KB </span>","children":null,"spread":false},{"title":"FIFO.vt <span style='color:#111;'> 1.45KB </span>","children":null,"spread":false},{"title":"FIFO.vo <span style='color:#111;'> 64.16KB </span>","children":null,"spread":false},{"title":"vsim.wlf <span style='color:#111;'> 2.38MB </span>","children":null,"spread":false},{"title":"msim_transcript <span style='color:#111;'> 2.39KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]